JPH0216052B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an output circuit configured with transistors and capable of automatically selectively extracting two types of signals depending on the external state of an output terminal.

The output circuit with a sensor has a pull-up resistor attached to the output terminal, or an open state (or a pull-up resistor and a pull-down resistor).
Vcc/2 state) and selectively outputs two types of signals.

This type of output circuit makes it possible to reduce the number of terminals in a digital circuit device, and is therefore extremely effective in designing highly integrated semiconductor circuits.

An example of a conventional output circuit with a two-signal switching terminal having a transistor structure is shown in FIG. In FIG. 1, a first signal input terminal 1 is connected to a first input terminal of a two-input AND gate 4, and a second signal input terminal 2 is connected to a first input terminal of a two-input AND gate 5. There is. Further, the switching signal input terminal 3 is connected to a second input terminal of a two-input AND gate 4, and is also connected to a second input terminal of a two-input AND gate 5 via an inverter 6.

The outputs of the two-input AND gates 4 and 5 are transferred to a two-input OR gate 7, and the output of the two-input OR gate 7 is supplied to the base of a transistor 8. transistor 8
The emitter is grounded, and the collector is connected to output terminal 9.
The output type is an open collector type.

The output is an open collector type, so when using it, please use it as an external component.
A resistor 10 (a so-called pull-up resistor) is used connected to a high potential (for example, 5V).

In such an output circuit,
The pulses shown in Figure c are respectively
When inputting to signal input terminal 1, second signal input terminal 2, and switching signal input terminal 3, switching signal input terminal 3
“L” level (waveform “L” level in Figure 2 c)
In the period where is input, the "L" level is applied to the second input terminal of the two-input AND gate 4, and the "L" level is applied to the second input terminal of the two-input AND gate 5, which is inverted by the inverter 6. "H" level is input.

As a result, the waveform shown in FIG. 2a input to the first signal input terminal 1 is inhibited by the 2-input terminal AND gate 4, and the waveform shown in FIG. 2b input to the second signal input terminal 2 is inhibited. Pulse is 2 input AND
It is selected by gate 5 and output to the base of transistor 8 through two-input OR gate 7.

The second input to the base of this transistor 8
The waveform in FIG. b is then inverted and output from the output terminal 9.

Here, when the signal at the switching signal input terminal 3 changes from "L" level to "H" level, two inputs
The pulse shown in FIG.
The signal is selectively outputted to the base of the transistor 8, inverted by the transistor 8, and outputted to the output terminal 9.

Also, at this time, the second
An "L" level signal inverted by the inverter 6 is applied to the input terminal, so that the second
Pulse applied to signal input terminal 2 (Fig. 2b)
is prohibited by this two-input AND gate 5.

As described above, one of the signals input to the first signal input terminal 1 and the second signal input terminal 2 is selected depending on the level input to the switching signal input terminal 3, and is inverted by the transistor 8. ,
It will be taken out from the output terminal 9. The signal taken out from this output terminal 9 is shown in FIG. 2d.

However, the output circuit shown in Figure 1 above requires a switching signal input terminal 3 in order to select between the two output signals.
When used in an IC, the number of pins on the IC increases, and in particular,
For products with 14, 16, and 18 pins,
Not only does this result in an increase in IC cost, but also an increase in area when actually attached to a board, which can lead to fatal flaws in terms of IC specifications.

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional method, and it distinguishes the external state of the output terminal by attaching an identification circuit to the output terminal itself without using an input signal switching terminal, and distinguishes between two types of signals. When used in an IC, it is possible to reduce the number of pins on the IC, which reduces the cost of the IC.
It is an object of the present invention to provide an output circuit that has advantages such as being able to reduce the area occupied when an IC is attached to a substrate.

Embodiments of the output circuit of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit diagram showing one embodiment thereof. In FIG. 3, the first signal input terminal 11 is the first signal input terminal of the two-input AND gate 14.
The second signal input terminal 12 is connected to the first input terminal of a two-input AND gate 15.

The outputs of the AND gates 14 and 15 are both input to a two-input OR gate 16, and the output of this OR gate 16 is sent to the first input terminal of a two-input AND gate 43. There is. The output of the AND gate 43 is the transistor 17
It is becoming possible to add it to the base of

The emitter of the transistor 17 is grounded, and the collector is connected to the output terminal 18 and to the connection point P ₁ between the resistors 21 and 22. The connection point _P1 is a resistor 21, a diode 25,
26 to the base of a PNP transistor 27, and a resistor 23 is connected between the base and emitter of this transistor 27.

Further, the connection point _P1 is connected to the base of an NPN transistor 28 via a resistor 22, the base of the transistor 28 is grounded via a resistor 24, and the emitter is directly grounded.

A voltage of +Vcc is applied to the emitter of the transistor 27, and a voltage of +Vcc is applied to the collector of the transistor 28 via a resistor 33. The collector of this transistor 28 also has two inputs.
It is connected to the second input terminal of the NAND gate 37, and also has two inputs via the inverter 35.
It is connected to the second input terminal of AND gate 36.

The collector of the transistor 27 is connected to the base of an NPN transistor 31 via a resistor 29. The base of the transistor 31 is the resistor 30
is grounded through the terminal, and the emitter is directly grounded. A voltage of +Vcc is applied to the collector of this transistor 31 through a resistor 32 and is connected to the first input terminal of an AND gate 36. Further, the collector of the transistor 31 is connected to a first input terminal of a NAND gate 37 via an inverter 34.

The output of AND gate 36 is the data flip
D of the flop circuit 41 (hereinafter simply referred to as FF)
Connected to the terminal (data input terminal). In addition, the output terminal of the NAND gate 37 has two inputs.
It is connected to a first input terminal of NAND gate 38. A second input terminal of this NAND gate 38 is connected to the control signal input terminal 13.

The output terminal of the NAND gate 38 is an inverter 39
is connected to the first input terminal of the two-input AND gate 40 via the AND gate 40.
It is connected to the second input terminal of 3.

A second input of AND gate 40 is connected to clock input terminal 42. This AND gate 4
The output terminal of 0 is connected to the clock input terminal of FF41. The output terminal Q of FF41 is AND gate 1
4, and is also connected to the second input terminal of AND gate 15 via inverter 19.

AND gates 14, 15, inverter 19, OR
The gate 43 constitutes a switching block 44, which includes diodes 25, 26, resistors 21-24,
A bias circuit 45 is formed by the transistors 27 and 28.

Also, resistors 29, 30, 32, 33, transistor 31, inverters 34, 35, 39, AND
Gates 36, 40, NAND gates 37, 38,
The detection circuit 41 is constituted by the FF 41.

Note that 20 is a pull-up resistor, one end of which is connected to the output terminal 18, and a voltage of +Vcc is applied to the other end.

Next, the operation of the output circuit of the present invention constructed as described above will be explained with reference to the waveform diagrams of FIGS. 4a to 4e. In this Figure 4,
T ₁ is the case when the output terminal 18 is open, and T ₂
shows the state when the pull-up resistor 20 of the output terminal 18 is connected.

4a to 4d are the first signal input terminal 11 and the second signal input terminal 1 in FIG. 3, respectively.
2. This shows the signals to be applied to the control signal input terminal 13 and the clock signal input terminal 42, and a to d in FIG. 3 indicate that signals having the waveforms of FIG. 4 a to 4 d are input. ing.

First, when the output terminal 18 is used in an open state, the transistors 27 and 28, the diodes 25 and 26, and the resistors 21 and 22 of the bias circuit 45 operate when the transistor 17 is on or during the time.
Approximately Vcc/2V {(Vcc/2-1.4V if the resistors 21 and 22 have the same value)} is generated at the output terminal 18. Note that the resistors 23 and 24 operate as bias potential resistors for the transistors 27 and 28.

In this state, both transistors 27 and 28 are turned on, and the collector of transistor 28 has an "L" level, and the collector of transistor 27 has an "H" level. The "H" level potential of the collector of the transistor 27 becomes the on-potential of the transistor 31 through the resistors 29 and 30, turning the transistor 31 on.

As a result, an "L" level is generated at the collector of the transistor 31, and the "L" level generated at the collectors of the transistors 31 and 28 is decoded by the inverters 34, 35, the AND gate 36, and the NAND gate 37, and the AND gate The output of NAND gate 36 becomes "L" level, and the output of NAND gate 37 becomes "H" level.

The "H" level output of the NAND gate 37 is transmitted to the first input terminal of the NAND gate 38.
Since the "H" level is input to the normal control signal input terminal 13, the NAND gate 38
The output of is at "H" level, and this "H"
A level is applied to the second input of AND gate 43, and a "L" level is applied to the first input of AND gate 40 through inverter 39.

Therefore, the output signal of the OR gate 16 applied to the first input terminal of the AND gate 43 is applied as it is to the base of the transistor 16, inverted by the transistor 17, and outputted to the output terminal 18.

Also, since the output of the AND gate 40 is at "L" level, the FF 41 does not read the signal from the D terminal.
Either the "H" or "L" level is continuously output to the output terminal Q, and one of the signals input to the first signal input terminal 11 or the second signal input terminal 12 is selected by the AND gates 14 and 15. The signal is then inverted by the transistor 17 via the OR gate 16 and the AND gate 43, and outputted to the output terminal 18.

However, when the "H" level is input to the control signal input terminal 13, the output of the NAND gate 38 becomes "L" level during the period in which this "H" level is input, and the output of the AND gate 43 becomes "L" level. ” level, and the transistor 17 is turned off. Therefore, the output terminal 18 is always connected to the above-mentioned level until the control signal input terminal 13 becomes "L" level again.
Vcc/2V is generated (ie transistor 17 is latched off).

Also, the output level of the NAND gate 38 (“L”
level) is inverted by the inverter 39 and the "H" level is transmitted to the first input terminal of the AND gate 40. Therefore, at this time, when the "H" level is input to the clock signal input terminal 42, this signal is input to the clock input terminal of the FF 41.

FF41 changes the level of the D terminal (“L” level) at the rising edge of the pulse input to the clock input terminal.
is read and output, so in this case it is at the "L" level.

Since this signal is transmitted to the second input terminal of the AND gate 15 through the second input terminal of the AND gate 14 and the inverter 19, the signal from the first signal input terminal 11 input to the first input terminal of the AND gate 14 is transmitted to the second input terminal of the AND gate 15. (FIG. 4a) is inhibited by this AND gate 14.

Also, input from the second signal input terminal 12
Signal at the first input terminal of AND gate 15 (Fig. 4b)
is selected by this AND gate 15, and
The signal is outputted from the gate 15 and applied to the first input terminal of the AND gate 43 through the OR gate 16.

Here, if the signals input to the clock signal input terminal 42 and the control signal input terminal 13 go to the "L" level, the output of the NAND gate 38 goes to the "H" level, and the second input terminal of the AND gate 43 also goes to the "H" level. ' level. Therefore, the OR gate 16 input to the first input terminal of this AND gate 43
The output signal is transmitted to the base of the transistor 17, and the inverted signal is taken out from the output terminal 18.

Further, the clock input terminal of the FF 41 becomes "L" level, and reading of data from the D terminal is prohibited. This completes one cycle, and the same operation is repeated thereafter.

That is, when the output terminal 18 is used in an open state, the signal input to the second signal input terminal 12 is selected, and this signal is output in the opposite phase.
This output waveform is shown at T ₁ in FIG. 4e.

Next, the operation when the pull-up resistor 20 is connected to the output terminal 18 will be explained. When the transistor 17 is not turned on, a potential is generated at the output terminal 18 by the built-in bias circuit 45 and the external pull-up resistor 20. This potential is Vcc−3×V _BE
≒Vcc-2.1V or more, transistor 27
is off, transistor 28 is on, and an "L" level is generated at the collectors of transistors 27 and 28.

At this time, the diodes 25 and 26 are connected to the output terminal 1.
When the pull-up resistor 20 is attached to the pull-up resistor 8, it is used to widen the potential at which the transistor 27 is turned off, and the number can be increased or decreased depending on the power supply potential used.

The level of the collector of transistor 27 is "L"
Due to this level, the transistor 31 is turned off, and the collector of the transistor 31 becomes "H" level.
Therefore, it is decoded by inverters 34, 35, AND gate 36, and NAND gate 37,
The outputs of the AND gate 36 and the NAND gate 37 become "H" level.

Thereafter, in the same way as when the output terminal 18 is opened, during the period in which the "H" level is input to the control signal input terminal 13, the output of the NAND gate 38 becomes "L" level, and the transistor 17 is turned on. AND gate 4 is configured to prohibit the
0, decoded by inverter 39.

As a result, at the rise of the "H" level input to the clock signal input terminal 42, the FF 41 is
Read the terminal level (“H” level) and set it to “H”
The level is output from the output terminal Q. The "H" level output of the output terminal Q is applied to the first input terminal of the AND gate 14, and is inverted by the inverter 19, and the "L" level output is applied to the second input terminal of the AND gate 15.

As a result, the signal input to the second signal input terminal 12 by the AND gate 15 is prohibited. Further, the signal shown in FIG. 4a input to the first signal input terminal 11 is selected by the AND gate 14,
It is sent through the OR gate 16 to the first input of the AND gate 43.

Here, the signals input to the control signal input terminal 13 and the clock signal input terminal 42 are set to "L".
level, the output of the NAND gate 38 becomes "H" level, and this "H" level is transmitted to the AND gate 43, so that the signal shown in FIG.
4a from the output terminal 18.
A signal with the opposite phase of is extracted.

Therefore, a pull-up resistor 2 is connected to the output terminal 18.
When 0 is connected, the signal input to the first signal input terminal 1 is selected, and this signal is output in reverse phase. The waveform of this output signal is shown in section T ₂ in FIG. 4e.

Note that when the transistor 17 is on, the "L" level is generated at the output terminal 18, and the transistor 27 is on and the transistor 28 is turned on.
is turned off, so an "H" level is generated at the collectors of both transistors 27 and 28. The "H" level generated at the collector of the transistor 27 turns on the transistor 31, and the "L" level is generated at its collector.

The level of the collectors of the transistors 28 and 31 is determined by the inverters 34 and 35, the AND gate 36,
It is decoded by the NAND gate 37, and the output of the AND gate 36 becomes "L" level, and the NAND
The output of the gate 37 generates an "L" level. Since this level is transmitted to the first input terminal of the NAND gate 38, the output level of the NAND gate 38 becomes "H" level regardless of the level of the control signal input terminal 13 (control signal input terminal 13, clock Since the signal at the signal input terminal 42 is ignored), the presence or absence of the pull-up resistor 20 at the output terminal 18 is not determined, and no malfunction occurs.

As described above, according to the output circuit of the present invention,
A bias circuit that applies a bias potential to the output terminal is connected, and a detection circuit detects the external state of the output terminal according to a change in the output level of the bias circuit. Since the output of the switching block that selects one of the signals input to the signal input terminal is switched, when two types of signals are selectively extracted from one output terminal, it is possible to use the conventional signal switching input. Terminals are no longer required.

Along with this, when used in IC etc.
It is possible to reduce the number of IC pins, which makes it possible to reduce the cost of the IC, and also to reduce the area occupied when the IC is mounted on the board.It also has advantages such as being usable for all ICs. has.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional output circuit, FIGS. 2a to 2d are signal waveform diagrams of various parts of the output circuit of FIG. 1, and FIG. 3 is an embodiment of the output circuit of the present invention. The circuit diagrams shown in FIGS. 4a to 4e are signal waveform diagrams of various parts of the output circuit shown in FIG. 3, respectively. 11...First signal input terminal, 12...Second signal input terminal, 13...Control signal input terminal, 14, 15, 3
6,40,43...AND gate, 16...OR gate, 17,27,28,31...transistor, 1
8... Output terminal, 19, 34, 35, 39... Inverter, 20... Pull-up resistor, 25, 26... Diode, 37, 38... NAND gate, 41... Data flip-flop circuit, 42... Clock signal input terminal, 44... Switching Block, 45...bias circuit, 46...detection circuit.

Claims (1)

[Claims] 1 A switching block that selects either the signal at the first signal input terminal or the signal at the second signal input terminal and outputs it to the output terminal in an open state or a pull-up state, and a bias circuit that applies a bias potential to the output terminal. , detects the potential of the output terminal based on the varying output level of the bias circuit, a clock signal, and a control signal depending on whether the output terminal is in an open state or a pull-up state, and selects one of the above signals for the switching block. The output circuit consists of a detection circuit and an output circuit.