JPS58114623A - Digital-to-analog converter circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (Technical field) The present invention relates to a digital-to-analog conversion circuit.

In particular, the present invention relates to a digital-to-analog conversion circuit suitable for application to a monolithic integrated circuit configuration.

(Background technology) As is well known, digital-to-analog converter (hereinafter referred to as D
AC) has a wide range of applications.

One type of DAC in integrated circuit l#% (IC) configuration is.

Contains an R-2R resistor ladder network. According to such a ladder network, a current is generated in the first branch of the network, and the current through the successive branches decreases in a ratio of 2:1, thus the ladder network has a 12 iK binary - A current having a weight of (this is called a binarized current) is generated.

The four binary weights generated at each branch of the ladder network are each coupled to a switch.

Each switch is selectively activated or deactivated in response to a corresponding pit of the digital word to be converted to selectively couple or decouple current to the output bus depending on the logic state of the bit. Thus, currents of binary type are selectively coupled to the output bus and thereby combined to produce a resultant current proportional to the digital word to be converted over the output bus. As the resolution demands on the DAC increase, the number of bits in the digital word to be converted increases, and the accuracy of the current produced in the first leg of the R-2R resistor ladder network increases accordingly. becomes even more strict. For example, the above-mentioned 1.i.

12-bit D using Ft-2B resistor ladder network
In an AC, the N degrees of its first branch resistance must be kept accurate to within 0.02 of its ideal value.

One technique suggested to reduce the required high accuracy of the first resistor of the R-2R ladder network is
N identical current sources must be provided, where N is the number of points in the digital word to be converted. However, when a 12-bit signal and AC are required, a relatively large number of 11151#s are required, so B-2R is used to convert the lower bits of a digital word (for example, the lower 9 pits of a 12-bit digital word).
It has been proposed to use a ladder network for which eight constant currents are used for converting the three most significant bits of the digital word. The current selectively coupled to the output bus from the eight constant currents for the top three pins is R-28.
The ladder is summed with 1a occurring at a branch of the network and selectively coupled to the output bus corresponding to the lower 9 bits of the digital word, so that the total ta generated through the output bus based on the stacking is will be proportional to the total 12-bit digital word. According to such a configuration.

Any error in the level of tfi produced by any one of the eight constant ttlt sources will reduce the accuracy of the DAC. Therefore, in order to realize the full benefits of this technique, the switch circuitry used to couple a selected one of the eight current sources to the output bus must have an error in the level of current produced by the current source. It should be set to 5 so that it does not cause this.

However, conventionally proposed switching circuits cause a difference in Ki when generating a desired output current. The source of errors in such switching circuits is that the actual current source generally has a finite output voltage, so the actual current supplied by the current source is proportional to the voltage supplied to its output terminal. get up. According to the proposed switching circuit, the voltage supplied at the output of each current source is a function of the logic state of the bits of the digital word to be converted, in which case the current value generated by the current source is Another source of error that occurs with this switching circuit when generating the correct current through the output bus, which is not independent of the digital word, is that the current supplied by each current source corresponds to the digital word to be converted. 0 passes through separate electrical paths to the output ''. Each electrical path includes an active NPN) transistor, in which case the transistors in the separate electrical paths are different. (the gain ratio of emitter current to collector current), and the bits of the digital word flow into the pace electrode of the transistor in question and the current generated by the current source outputs through the emitter-collector electrode of the transistor in its path. Because it flows to the bus.

This current source causes the current value actually contained in the total of 11 currents flowing through the output bus to be responsive to the digital word to be converted. Furthermore, the proposed switching circuit generates a switching signal to the pace electrode of the transistor whose level changes depending on the digital word to be converted, and is responsive to this signal when a relatively large change in signal level occurs. The switching time of the transistor increases.

(Summary of the invention) A digital-to-analog conversion circuit according to the present invention.

A switching network selectively couples or decouples a selected one of the plurality of constant current sources to the output bus according to the digital word to be converted to generate an output current having a level corresponding to the digital word through the output bus. occurs. The circuitry selectively combines the bits of the digital word into lll1! a logic circuit that generates control signals for the plurality of control signals and makes the at least one control signal correspond to a plurality of bits of the digital word; and an Il number of switching transistors, each switching transistor corresponding to one of the plurality of control signals. Controls attached to things (
one (i.e., pace) electrode, one (i.e., emitter) electrode coupled to a corresponding one of the plurality of constant current sources, and a second (i.e., collector) electrode coupled selectively to the output bus. Sound.

The current source is selectively coupled or uncoupled to the output bus depending on a control signal directed to a control electrode of a transistor coupled thereto.

According to the invention, the logic circuitry generates a plurality of control signals with approximately equal switching level changes. Also, the IIIEE provided by each electric current is nearly independent of the digital word to be converted, so that the effect of output impedance on the level of 11:00 generated by the current is almost independent of the digital word to be converted. It becomes irrelevant. Furthermore, each constant current source, when coupled to the output bus in accordance with the digital word to be converted, always passes through the same transistor of the plurality of switching transistors, regardless of the digital word commanding this coupling. With such an arrangement, the level of current produced by each current source and its contribution to the total output current is independent of the digital word to be converted and the relationship of current level to the total current flowing through the output bus. is also independent of the digital word to be converted.

In a preferred embodiment of the invention, the logic circuitry is the first
, each logic gate being coupled to at least one bit of the digital word to operate an AND logic relationship and a complement logic function on that bit. Each of the logic gates is coupled to a corresponding one of the second plurality of current sources. A reference current source is coupled to the bias voltage through a resistor and produces a reference voltage across the resistor that is proportional to W* produced by the reference current source. The reference current source is thermally K and electrically matched to the second plurality of current sources. Each of the second plurality of current sources is coupled in series to the bias voltage bus through a resistor included in the logic gate. Depending on the bit of the digital word coupled to the logic gate, the resistor generates a logic signal representing the logic state of the bit of the digital word coupled to the gate. Since each of the second plurality of current sources is matched to a reference current source, the resistor coupled to the reference current source is chosen to be the negative of the resistor included in the logic gate, thereby making the resistance of this gate The state of the logic signal generated by the logic signal is determined by whether the level of the logic signal is higher or lower than the reference voltage. The second plurality of logic gates is provided with a logic signal generated by the first plurality of logic gates and based on the logic signal, the N0F
(and 0Rfi calculation. The second plurality of gates each have a threshold level tE, and the base voltage is generated by the first plurality of logic gates.

The plurality of gates in isolation generate control signals for the switching transistors. The logic state of each control signal is the first
is determined by the relationship between the level of the logic signal applied by the plurality of logic gates to the second plurality of logic gates and the level of the reference voltage. In this way, the threshold level used to generate the logic state of the control signal is generated by the reference voltage fIL source which is thermally and electrically matched to the second plurality of 11 sources as described above. be done.

(Explanation of Examples) An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 1, a 12-bit digital-to-analog converter M (DAC) 10 is shown, which DAClo consists of a reference resistor 16 coupled to a reference voltage source +VR, . It includes a current source 14, a computational amplifier 18, and a transistor 20 and a resistor 22 configured to generate a reference current through a reference resistor 22 as shown. A plurality of transistors Q, -Q8 have their pace electrodes connected to the pace electrode of transistor 20 as shown. The emitter 1 poles of the transistors Q1 to Q8 are connected to -Vo through the corresponding resistors R. [source? In this case, it is connected to -15 (V). Here, the emitter area of the transistor 20 (represented by the symbol 4x) is four times the emitter area of each transistor Q, ~Q8 (represented by the symbol X), and since the resistance value of the resistor 22 is 7, each transistor Q, The current flowing through the collector electrode of ~Q8 will be equal to 1 of the reference current IR. Thus, a plurality of transistors Q, ~Q8 in this case eight constant current sources I, ~
It consists of 18.

Constant current source 1. ~I7 are respectively connected to corresponding ones of seven pairs of switching transistors Qa, Qa' ~Q, , Q, , ', and the current source circuit is Fl-2B resistor ladder digital-to-analog conversion circuit W8CDAIC) section 3[1 It is connected to the. Switching transistor QalQa'~
The control life of the pace electrodes Qg and Qg' is 27a.

27a' to 27g are connected to the increment Itm buried section 26 through 27g' and connected to the bus 28 through a bias resistor RB having a value equal to 1. bus 28
A bias voltage VB is connected to. One transistor of each transistor pair in this case Qa to Qf and Qg
The collector electrode of Qa' to Qf' and Qg is connected to the output bus 1° through a resistor R8, and the collector electrodes of the other transistors of each transistor pair, Qa' to Qf' and Qg, are connected to the output bus 1°. K is connected. Here, a further resistor R is connected to the collector electrode and the output bus l. included in between. Top 3 digital words to be converted) B, B, B (
Of these, B1 is the most significant bit (MSB)) is coupled to increment logic 26. The lower pitch of this digital word F B
4 T B s * B s * 87 * B s
+ B s + B 1ow B 11 T B 1
□ (of which B1□ is the lowest pitch (LSB))
is coupled to an R-28 resistor ladder circuit digital-to-analog converter (DAC) section 60.

Current ill, ~1 in response to bits B, B, and B
The selected books out of 71 2 3 are the output bassue. combined with.

The remaining books of current source ■ and ~1□ are output bus l. , which is coupled to bus K from bus l. The sum of the currents coupled to bus 1° is proportional to the three most significant bits of the digital word, and the sum of the currents coupled to bus 1° is proportional to the complement of the three most significant bits of the digital word. The current source 18 has R-2 as a reference current.
An R resistor ladder is applied to the network DAC 30 (described in detail below). But here, the switches 328-621 are respectively 1[flL source l,'-1. ′. The switches 32a-62i selectively connect the output bus 1° or 1 depending on the logic state of the bit that causes the current switching to 1. is a known current switch similar to that shown for switch 32a coupling a current source to either of the two. obey [
Each current switch includes a pair of transistors.

The base electrode of one of the transistors is the base voltage ■B,
(1.4 (V) in this case) and the pace electrode of the other transistor is connected to the bit of the digital word to be converted. where a logic ``1'' couples the current source drawn into the switch in question to the output bus 1.1, and a logic ``0'' couples the current source drawn into the switch into bus 1. join to. Next Lt[fi source 1. /~1. ′
and the output bus l. The sum of the K-coupled currents is proportional to the lower bit portion of the digital word (ie, bits 84-B1□).

Also, current source 1. The sum of the currents generated by '~l, / and coupled to the output ear is proportional to the complement of bits B, ~B12. Using overlapping filling, the tfi of bus 1°
It can be seen that the level of is proportional to the 12-bit digital word, and the current level of bus 1° is proportional to the complement of the 12-bit digital word.

The increment logic section 26 (described in detail later with reference to FIG. 2) outputs the logic state of the selected combination of B, +B2 and B3 to the control lines 27a, 27a' to 27g, 27.
Generate a logic signal on g'. moreover.

The control signals for the control lines 27a, 27a'-27g, 27g' are shown in Table 1 below. Here, "E+" represents the logical correlation number, "・" represents the logical product function, and "-
” represents a complement function.

TABLE 1 Thus, the logic signal is applied to control line 2 in response to bits B, 1B21B3 of the digital word as shown in Table 2.
7a, 27a' to 27g, 27g'.

Let me clarify about Figure 2 here.

- The logic "1" signal is on the control line 27 a-v 27 a'
When ~27g = 27g', the switching transistors Qa, Qa/~Qg -Qg' connecting the pace electrode to this control line are biased into conduction, and the coupled current source, ~17 passes through the output bus 1°, 1oK to which is connected. Therefore, the current -1~
It can be seen that bits B, lBz+B, and vc are selectively coupled to either bus 1° or 1° as shown in Table 6 below.

Therefore, B2. As a function of B, the constant current #
Bus I from 11 to I (each generating electric current). and l. 'The total current flowing with different Ik is the fourth
The result will be as shown in the table.

Table 4 Thus, the increment logic unit 26 outputs 2H levels of voltage fi (N is the number of bits of the digital word applied to the logic @26) to the line e. By coupling to K, the total current is proportional to the digital word represented by N pinto.

In addition, one of the current sources I, to I7 is output to the bus ■.・Eng.

It can be seen that the current source always passes through the same switching transistor corresponding to each of the 2H digital words applied to the logic section 20 that are coupled into one. Thus, for example, the digital word (0)1o~(
3) Current source works in response to 1°.

is coupled to output bus 1 DEG and in response to each generated digital word current source 1 passes through the same switching transistor Qd'. Similarly, current source 2 is connected to the output bus 1°K in response to the digital word (21, o to (7), o), and current source 12 is connected to the output bus 1°K in response to each digital word generated. The output bus 1°K is passed through the switching transistor, namely the switching transistor Q. In this way, the current drawn into the total current generated through one of the output buses by one selected current source is connected to this selected current source. current source is always (
b) Since it is coupled to the output bus through the same switching transistor, the β of the other switching transistor is
Not affected by Furthermore, transistors Qa and Q a
Considering /, it can be seen that the voltages at the emitter electrode and the collector electrode of the transistor Q here are equal to -■, if we ignore that this transistor is conductive. Here ■□ is the voltage drop between the pace and emitter of the conducting transistor.

It is about 0.7 [V]. Thus the current source 1. The voltages supplied to 911 to 1. are completely independent of the digital word to be converted, and the currents 911 to 1. The effect that the output impedance of IIP on the current actually produced by the current source IIP is independent of the digital word to be converted.

In FIG. 2, the detailed configuration of the increment logic circuit network 26 is shown in the AND-NANDlliii buried gate section 42 and the 0H
-NOFt gate section 44 is included. AND complement complement 1 game filling gate 2 is 6 AND games)
46, 47.48 and 6 inverters 49.50.5
1. Gates 46 to 48 and inverter 4
9 and 5.1 each have a unique configuration. Gates 46-48 and inverters 49-51 are connected to PNP reference transistors 52-57 and PNP input transistor 52.
a, 52b.

53a-53b, 54a, 54b, 55a, 56a, 5
71. Transistor 52 of AND gate 46.
52a and 52b share the emitter electrode with the terminal 60aK.
transistor 53.53a of AND gate 47
, 53b have their emitters commonly connected to the terminal 60b, and AN
Transistors 54, 54a and 54b of the D gate 48 have their emitters commonly connected to the terminal 60c, and transistors 55, 558 of the inverter 49 have their emitters commonly connected to the terminal 60c.
d and the transistor 56.56 of the inverter 50
8 has its emitter commonly connected to the terminal 606, and transistors 57 and 57a of the inverter 51 have their emitters commonly connected to the terminal 606.
Connected to m child 60f. Bit B1 is coupled to the base electrodes of transistors 52b, 54b and 57g, and bit B2 is coupled to the base electrodes of transistors 53a.

Bit B is coupled to the pace electrodes of transistors 54a and 56a, and bit B is coupled to the base electrodes of transistors 52a, 53b and 355a. The collector electrodes of the reference transistors 52 to 57 are connected to a load resistance RL of equal value.
It is connected to bus 64 through.

Transistors 52a, 52b, 53a, 53b and 54
The collector electrodes of a and 54b are directly connected to the bus 64. Transistors 55a, 56a, and 57a are connected to bus 64 through a load resistor R□ whose value is equal to the load resistor RL described above. Bias voltage V = (-Vo
. +1.4) (V) is connected to the bus 64. The electric currents 60a to 60f are connected to constant current sources 1a to 1f, respectively, and this constant tK source has its base electrode connected to the bias tEEVB□. +■ooI emitter electrode
connected to the source (here ■B 2” +V oo V
BIt+vo. =5 [■]) Transistors 70 to 75
Contains. The reference transistor 78 has a base electrode connected to the base electrodes of the transistors 52 to 57, and one emitter pole connected to the IIr current source 1. '()/The resistance value of the resistor containing the raster 80 is the resistance value i of the load resistor RL) 80 connects the emitter electrode to the bus +■. 0, and its base electrodes are connected to the base electrodes of transistors 70-75. Further, a transistor 8o is formed in a part of 1G, and this IG
DAClo is formed close to where transistors 70 to 75 are formed, so that the temperature (or heat) and electrical characteristics of transistor 8o are the same as transistor 70.
Thus, the current generated through the collector electrode of transistor 80 is approximately equal to the current generated through the collectors of transistors 70-75. Therefore, the voltage V1/2 (approximately 10
If 0(100() is generated across the load resistance, SI, then the voltage .
1 reference B 2! The logic "1" signal of B3 is represented by a voltage larger than ■B1 (i.e., t4 (V)),
A logical rOJ signal is also represented by a voltage less than 11.4 (V). Therefore AND gate 4
6.47.48 to the base electrode j of a pair of input transistors (both given bits are logic “1”)
” signal, the reference transistor of the AND gate in question generates rHJ or a logic “1” output voltage (■, +vB3) at its collector through four, whereas one of the pair of bits is a logic “ 0'', the transistor to which this logic signal is applied becomes conductive, and the input transistor of the AND gate becomes non-conductive.

rLJ or a logic "0" output voltage (■B3) is generated at the collector electrode of the reference transistor.

As a result, 1MA buried] 0'' signal is Inno (-E 56, 57
58. Any one input transistor 56a.

57a, 58a to make the input transistor conductive and generate an "H" or logic "1" voltage at its collector electrode ("complement" operation), Then rLJ or logic “0” voltage vB3 is generated at the collector of the non-conducting reference transistor of the concerned I/N (“true” operation).
. On the contrary, if the input signal to the base of the input transistor of the 4-inverter is a logic "0" signal, then
The input transistor is conductive and its collector electrode has II-
IJ-r, or a logic "1" voltage (V, +VB,), is generated, whereas the reference transistor of the inverter produces rLJ, or logic rOJ, at its collector electrode. As a result, AND gate 46°4
7.48 The voltage across any one of the load resistors.

Alternatively, the fluctuation occurring in the voltage across one thread of the load resistance RL of the inverter is V, (V), which follows the voltage fluctuation occurring across the low load resistance RL.

Since the transistor 80 follows this temperature change, the current tl
There is a possibility that the L sources 1a to 1, and in this case the current @l,' will be affected. ANI) The logic signals generated by the gates 46, 47, 48 and the load resistor HL of the inverter 49, 50, 51 are summarized in Table 5.

Table 5 0R-NOR gate section 44 has seven gates 1100a-
Contains 100. Gates 1003 to 100g each have a similar configuration. Goo) 100a~100g
are NPN reference transistors 101 to 107 and NPN input transistors 1ff1a, 101b, 101c, 10
2a, 102b, 103a, 103b104a, 105
a, 105b, 106a, 107as107b, 107
Contains c. Reference transistors 101-107 have their collectors connected to control lines 27a-27g, respectively. Goo) iota transistor 101a = 101
b, 101c connect the collector electrodes to the control line 278', and the transistors 102a, 102 of 1DOb
Transistors 103a and 103b of 100c have their collector electrodes connected to the control line 27C', and 10
The transistor 104a with a gate 100e has one collector connected to the control line 27d' and a transistor 104a with a gate 100e.
05a, 1 osb connects the collector electrode to control line 2
7e' and a transistor 106 with a gate 100f.
A has a collector electrode connected to the control line 27f', and transistors 107a, 107b, 107 with a gate 100g.
c connects the collector electrode to the control line 27g'.

The emitter electrodes of the transistors 100a to 100g are connected to a corresponding one of seven constant currents -IR' in this case. Here, this 'wra source includes transistors 1083-108g. The base electrodes of the transistors 1083 to 108g are connected in common and a bias voltage V3. (In this case -vo.+[L7(V
)), and the air terminal electrode is connected to the -voo bus. The collector electrodes of transistors 1083-108g are connected to gates 1003-100g, respectively. AND-complement logic gate section 42 performs 0R as follows.
- a reference voltage VB coupled to the NOR gate section 44, i.e. generated at the collector of the transistor 78v1, 109
are applied to the base electrodes of reference transistors 101-107 via the reference transistors 101-107. The base electrodes of the transistors 101a to 107c are connected to the AND-complement logic gate s42 according to Table 6.
are connected to output lines 90-98 of.

The reference voltage applied to the transistors 101 to 107 in Table 6 is generated on the line 109, and since this voltage is the intermediate value of the voltage fluctuation of the signals on the busy lines 91 to 98 as described above, any of the voltages 100a to 100g When any one of the input transistors is applied to the pace electrode with a voltage greater than the base voltage of line 109, that transistor becomes conductive.

The reference transistor of the gate in question is not conducting and the current flows through the bias resistor R1 connected to the conducting input transistor, which input transistor is connected to the pace electrode of the switching transistor connected to it (by generating an LJ voltage). This switching transistor becomes non-conductive.

In response, the EHJ voltage is developed at the other pace electrode of the pair of switching transistors, causing that transistor to turn on, or conductive. On the other hand, if the signal applied to the pace electrode of one input transistor of gates 100a-100g has a voltage less than the line 1090 reference voltage, all input transistors of that gate will be non-conducting. , the reference transistor of that gate conducts and a "H" voltage is developed at the pace electrode of the switching transistor connected to the input transistor of that gate, thereby switching the switching transistor into conduction, whereas The other one of the switching transistors will apply the jLJ voltage to its pace electrode, and the switching transistor will then be biased into a non-conducting state. As a result, the collector electrodes of the reference transistors 100a to 100g perform an OR logical operation.

Further, the collector electrodes of the input transistors 101b to 107C are subjected to NOR@OR logical operation. As a result, the logical expressions shown in the above-mentioned Tables 5 and 6 to the above-mentioned Table 1 are subjected to complement calculation by the increment logic section 26.

Referring again to FIG. 1, the R-2B resistor ladder circuit network Dj1
30 is shown in detail, the master ladder circuitry 200
and a slave ladder network 202 coupled together and provided with a current source 18 through an input 204. Thus, master 1 da-times i-net 200
is a transistor 210a-2 with a common pace electrode coupled to a bias voltage vB5 (-5 (V) in this case).
12-210be214-216.218 and 220 are connected, and their emitter electrodes are coupled to bus 222 as follows. Transistors 210a, 212 and 210
The emitter electrode of b is coupled to bus 222 and connected to transistor 2 through a resistor RLD of equal resistance t.
16 emitter electrodes are coupled to bus 222 through a shunt resistor 'LD and two series connected series resistors each having a resistance value LD and transistors 218 and 2.
Twenty emitter electrodes are connected to bus 222 through corresponding shunt resistors 2RLD and two series connected resistors 2RLD. The emitter region of the transistor/raster 220, designated Y, is the emitter region 4Y of the transistor 218, and the emitter region of the transistor 216 is 2Y.

The emitter region of transistor 214 is 4Y.

Each transistor 2105m, 210b and 2120 emitter area is 8Y. Transistor 210a.

Collector electrodes 210b are commonly connected to terminal 224. Terminal 224 is connected to switch 321, and collector electrodes of transistors 212-218 are connected to switches 32b-326KII, respectively. bus 22
2 is connected to the pace electrode of transistor 226 and the collector electrode of transistor 230. The pace electrode of transistor 230 has a bias voltage EEV, 'vcws
It is threaded.

The emitter electrode of transistor 260 is transistor Q8.
The collector electrode Kll is wired. transistor 22
The emitter electrode of 6.22B is connected to the collector electrode of the transistor 232. The emitter region of transistor 228 is 65Y.

Further, the emitter region of transistor 226 is Y. Transistor 262 connects the pace electrode to transistors Q, ~Q
8, and its emitter electrode is connected via a resistor 7 at C, -V0°K.

As mentioned above, the emitter area of transistor Q8 is X and the emitter area of transistor 262 is 2x. Transistor Q8 thus forms a single current source, so that current 2I passes through the collector electrode of transistor Q8. transistor 22
The collector electrode of 8 is coupled to a bias voltage VB through a resistor RT and a diode 234. Thus, the input section 204 is connected to the transistor 226°228.250,2
52. The transistor 230 includes a resistor R1 and a diode 264, and the transistor 230 is a transistor Qa-Qa' to Qg.Qg'.
Transistors 226 and 228 are used to compensate for the base current lost in transistor 210a.

210b, 212-220 and switches 32a-52i
used to compensate for the pace current lost in the switching transistor of the The current through the ml bus 222 is the five binary currents $1. '
~lS'. 2 clown fiI to enter,' is 2
transistors 2101 and 210bK are supplied,
This transistor is shown in FIGS. 7 and 8 below. Physically separated by transistor 212 when formed as a lCf1lili device as described with IO. Furthermore, the emitter voltage 11 of the transistors 210a and 210b
The connected resistors RLD are also physically separated from each other, and the resistor RLD connected to the emitter electrode of the transistor 212 is physically separated between the pair of resistors described above, as will be described later in conjunction with FIGS. 7 and 8. It is located in

! The star ladder network is defined as a current source circuit, 1, combined with the most significant bit (MSB) (in this case B), and a current source circuit combined with the '6' upper second bit (B, in this case). By composing K together, the primary heat generated in the IC chip in which DA (3) is formed.

Diffusion and/or sputtering and stress gradients are substantially canceled. 7 and 8, some details of the resistor circuitry coupled between the emitter electrodes of transistors 210g, 212, 210b, and 214 are schematically shown in FIG. It is formed on the IC substrate shown in the figure. As shown in FIG. 7, the emitter electrodes of transistors 210a, 212 and 210b are connected to bus 222 through resistors R, +Rz and R1, respectively, where the resistance value of each resistor R112 and Fl is RLD. The emitter of transistor 214 is connected to a first end of resistor R6, which has a resistance value RLD& as described above with respect to FIG. A pair of resistors Ras''' 4b connected in parallel are connected to the bus 222 and the second end of the resistor R3.
The resistance value of 4b is "LD".

It is. Next, regarding FIG. 8, the transistor 210a,
212.210b and 214 and resistance R, sR2+ R
The configuration of s*R4a*R4b and the resistor H on the IC board 215 is shown. Transistor 210a.

The collector regions of 212, 210b and 214 in this case consist of N-type conductive regions formed on substrate 215. Collector areas 217, 219, 221.

226 include P-type conductive space regions 225I22, respectively.
7.229.261 are being spread. Resistor R1# R
z t Rs * R4a r RaB and R6 can be formed as p-type conductive diffusion regions in an epitaxial layer, for example, by spucking thin film resistors formed on a substrate using known techniques as shown. base area 22
Annular emitter regions 233, 235, 237 and 269 are diffused within 5, 227, 229 and 231, respectively. Here, each transistor 210a, 212, 2
1. rJb has eight emitter regions and transistor 214 has four emitter regions. Contacts to the spacing areas of transistors 210a, 212, 210b are made by conductors 241. "sv vector region 217°2 of transistors 210a and 210b
21 are connected to terminals 224 through conductors 243 and 245, respectively.
It is connected to the. Collector regions 219 and 223 are connected to conductors 247 and 249, respectively. The eight emitter regions of transistors 210a=2121210b are connected to conductors 254, 256, . Through 258 [resistance R
1eR2*R3 is connected to the upper end 251.253.255. The transmitter region of transistor 21404 is connected through conductor 261 to the upper end 259 of resistor R5. The lower ends of the resistors R1sR2eR1wR, a+R, and B are each connected to the bus 222. Resistance R
The lower end 273 of 5 is connected to the resistor Ja+R1 through the conductor 279.
, is connected to the upper end of 275.277Kil.

By configuring in this way, the resistance R1# Rz +
The average sputtering or diffusion slope across Rs will be 5 such that the slope effect between resistors R3 and R1 is equal to the effect of resistor R2. Furthermore, each resistor R1・R, eR3
have the same resistance value and pass the same current value, so they consume power equal to 1 K. Thus, even though the known R-2B low resistance network DAC is used in the DAC:50 location, the DAC R0 compensates for thermal and sputtering gradients.

Slave circuitry 202 includes switches 32f to 32, respectively.
Transistor 24 with iK-coupled collector electrodes
0 to 246 and an output transistor 246 having a grounded collector voltage, lj. transistor 2
40 to 248 is the bias voltage vB6' in this case -2,
6 (V)) and a common base voltage coupled to the collector of coupling transistor 250, collector electrode K11ltll of transistor 220.

Further, the emitter electrode of transistor 250 is connected to the collector electrode of transistor 226.

The emitter regions of transistors 246, 248 are 2z, and the emitter regions of transistors 244, 242, 240 and 24 are
The 2 vine areas of 0 are 4Z, 8Z, 16Z and 3 respectively.
It consists of 2Z. The pace electrode of transistor 250 is coupled to the emitter electrodes of transistors 240-248 through a well-known resistor network in which a shunt resistor RL
D'&t) RLD' is connected to the emitter electrode of the Tunister 240.242, and the resistor - is connected to the binary voltage ff1l,'~
It is connected to supply l,1. Transistors 226 and 250 are designed to compensate for base current loss through transistors 240-248. Also, the output bias is 1° and the trunk XpQa~Qf and Qf'
The resistor R coupled between the collector electrodes of the transistor 210a is such that the resistor RLt connected to the emitter electrode of the transistor 210a produces the same voltage drop as the voltage drop produced across the resistor RLt.
, so that the effect of the finite output impedance is the same if we ignore the current path between the output bus and the current source that generates this current. The voltage vII is chosen sufficiently high so that V, -V□ is greater than the output of the amplifier 20. This prevents the current sources 11-1. The output conformance is selected to be sufficiently low.

In this case, VB is -6.8 (V), and the output of the amplifier 20 is -11.4 (V).

Turning now to FIG. 3, another embodiment of a 12-bit DJ 110' is shown. In this case 8 constant currents ill, ~
18 is a reference current source 14' (comprised of a reference resistor 16', an operational amplifier 18', a transistor 20' and a resistor 22') configured to generate a reference current II through a reference resistor 22' in a known manner. ).

A plurality of, for example, eight transistors Q1' to Q8/ are prepared and their pace electrodes are connected to the pace electrode Ii of the transistor 20'.
K is connected. The emitter electrodes of transistors Q'-Q' are connected to bus 24'KI' through corresponding resistors R'. In this case, the emitter area of transistor 20' is four times the emitter area of each transistor Q, / to Q, /, and the resistance of resistor 22' is T, so that.

The current flowing through the collector electrode of each transistor Q1' to Q, / has a value as strong as the reference current 11'.
Constant current sources I,1 to I,' are formed, respectively.

Each current source,'~I,t is 8 sets of switching transistors CQtIQt/ ) e (Q'be Q'b
t e Q'be ) glue (QIc@Q'c/ IQ',
#) e (QId*QIdt*Q', 1 #)
l (Q', #Qle/-Q', #) , (Q'
(-Q'p -Q'(e) -(Q'g, Q', t
*%, ) and (Q%, QIh/) are connected to the corresponding ones. The emitter electrode of each transistor included in each of the eight sets is connected to a corresponding one of the eight current sources 1' to 1'8. This transistor Q
The pace electrode of /, Q'h, is the control line 27'.

27'a' ” 27' a #~27',
277 t' respectively increment logic 26
' and to bus 28' through a resistor Rl/ of a different value. Bus 28' has a logic voltage vB
It is connected to I.

Transistor Q'aIQ'bI-Q'C# e Q'd
I# Q'e# e Q'(y and Q'g# Q Nerctor electrodes are connected to output bus 1 through resistor R0', transistors Q'b, Q'C, Q'l dQ/,
, Q/, , Q/, and Q'h are connected to the output bus I. ', and the transistor Q',/t
Q'ble Q'CtQ'd/ @ Q'e/ r
The collector electrodes of Q'7 and Q'hI are connected to the ladder one-way network bus LNB. The ladder network bus LNB is coupled to the R-2R resistor ladder network DAC 30' and the current on this bus LNB is the current 111 of FIG.
．． provides a reference current for ladder network 60' in the same manner as provided by . Upper 6 bits B1. B2. B
, (where B1 is the most significant bit) are coupled to increment logic 26'. Lower bits B, ~B
1□ (here 81□ is the least significant bit) is R-2R
A four-way ladder is coupled to a network DAC5Q/.

Bit B1. In response to B, eB3, current source 1, #, .
1, the selected one of t is coupled to the output path 1≦,
A selected one of the current source circuits #~, ' is coupled to the ladder circuit bus LNBK to the R-28 ladder circuit Dj13.
0/, and a current source l,'~1
．． ' is bit B of the digital word.
Basue proportional to B 2 + B 3. 'is the sum of the currents generated by the current sources coupled to the output path 5. The sum of the currents coupled to bus 1' by R-2 HDAC 3Q/ is proportional to bits 84-B,2 of the gain word. Similarly, the sum of the currents coupled to output bus 1' is proportional to the complement of the digital word K, equivalent to that described above for the 12 bits AClo of FIG.

But in this case the reference supplied to D A C3[1'
The I11 current consists of eight current sources, selected from 1 to 1. Details of the DAC 30' will be described later. However, what I will describe here is one of the eight current source works "~18',"
2 depending on the reference current supplied from 1 to DAC3Q'
), in this case switches 32a' to 32d
1 is shown in a two-pole configuration, a single-throw switch may be used in place of switch 32a in FIG.

The increment logic 26' (details of which will be described with reference to FIG. 4) is connected to the seventh
Occurs according to a logical state that selectively combines bits B, tB, and B3 as shown in the table.

Table 7 Thus, the control signals generated on control lines 27'a to 27'g/ in response to bits B1*B, B, are
It is expressed as shown in the table.

Furthermore, as is clear from Figure 4, 111 “fiI
f, sources 11'-18' are bit B at 5 as shown in Table 9;
・Selectively operate the bus 1゜' in response to B2 and B3. 'or LBN.

Therefore, as a function of B, tB, , B, constant current source 1
1' to 18' (each generating current level 1./) to bus l. 'sI. The total current flowing through LNB and LNB is K as shown in Table 10 below.

TABLE 10 Increment logic 26' thus generates a 2N level of current proportional to the digital word represented by N bits, where N is the number of bits of the digital word applied to logic 26'. Also, the logic section 26
′ for each of the 2 digital words applied to 8 currents f! #,l,'~1. ' are connected to the same bus l through the same switching transistor. '
sI. ' or LNBIC coupled, for example, a current source 1 is coupled to the output bus 7 according to the digital word (0) 1° to t2) 1°, and the current S is connected to the bus 1
0', the current generated by this current INK passes through the same number of switching transistors (switching transistor Q/d). Similarly, the current source 12y is coupled to the output bus 18' in accordance with the digital word (2) 1°~(katana,.), in each case the current source 1□
' passes through the same switching transistor (ie switching transistor Q/b).

Next, referring to FIG.
Details are shown including a second @IK designated AND-complement logic gate portion 42 and an 0R-NOR gate 44'. A reference voltage is therefore generated on line 109 and a logic signal is applied to bits B11B, B3 as shown in Table 5 above.
is generated on lines 90-98 in response to

0R-NOR gate section 44' includes six logic gates 100-1006 in addition to the seven gates 100a-100g described above with respect to FIG. Logic games 1001 to 1006 have the same configuration, and as an example, logic game 1001 is shown in detail, with three input quadrant sisters 1o.

111 and 112 and a reference transistor 16. Transistors 110, 111, 112 and 113
The emitter electrodes of the transistors 110, 111 and 112 are connected in common to the current source IB#, the collector electrodes of the transistors 110, 111 and 112 are connected to the control fi/27' ay K, and the collector electrode of the transistor 16 is connected to the bias voltage ■/,
It is connected to the. Transistors 110, 111 and 1
Twelve pace electrodes are connected to lines 97, 95 and 94 respectively.
It is connected to the.

Pace H1 of transistor 13 is coupled to bus 109 and provides a reference voltage generated by gate portion 42 as described above with respect to FIG. At this time gate 100
1 performs a NOR gate operation on the signals given to the pace electrodes of transistors 110, 111 and 112 based on the control life 27'l.

The gates 1003-100g are wired with lines 90-98KIi as shown in Table 6. Gate 100-10
The base electrode of the 060 input transistor is connected to lines 90-98 of the gate section 42 according to Table 11.

11th! ! The resultant logic signal is 5 on line 27 in response to bits B 1 + B 2 I B s as described above for Table 7.
'a, -27'2.

Regarding Figure 6, R-2R ladder circuit network L) AC3 []
/ includes master ladder circuitry 200 and slave ladder circuitry 202 of DAC 30 (FIG. 1), but in this case DAC 30' is transistor 226'ν228.
' , 232' = resistance R? / and diode 246'
204'. Thus transistor 2
32' is the pace electrode of the transistor Q and the pace R of the transistor Q8/
' Connect to the electrode and also connect the emitter electrode through the resistor.
connected to voo. The emitter region of transistor 232' has an area twice (2x) as the emitter region (3) of each transistor Q, /~Q8/. Thus, the current through the collector electrode of transistor 262' is 218! It is. Also, the ladder circuit network bus LNB is a transistor 226
', 22B' is connected to the pace electrode. Transistors 226', 228' have their emitter electrodes connected to collector 1[4k of transistor 232';
The emitter region of transistor 228' is 63Y;
And the emitter region of transistor 226' is Y.

The collector electrode of transistor 226' is connected to transistor 2.
50 (as in DAC 30 (FIG. 1)), and the collector of transistor 228' is connected to D
Diode 234' and resistor R as in the case of AC30
It is connected to the bias voltage V□ through T'. Transistors 226' and 228' are the transistors of master ladder network 200 and this master ladder network 20.
switching transistor (not shown) coupled to 0
Compensate for pace current loss caused by

Turning now to FIG. 5, a 14-bit DAC is shown with an incremental logic network 26' modified to provide control signals on lines 27Ia-27IO in accordance with Table 12, which control signals are provided in 15 pairs. each pair of transistors is connected to a constant current source l,
5 K drawn and constant current driver 116 changed R-
The 2R ladder is input to DAC 30# to convert the lower 10 bits of the 14-bit digital word.

Table 12 Next, in FIG.
116'. Lines: y'17'a-271d are applied to the transistors, and this control signal is generated by increment logic circuit 1126' according to Table 16.

! Ladder circuit network bus LNB' in Table 13 is a must! ! An R-28 ladder modified according to the circuitry DAC 30IN is coupled to generate a current on line LNB' and a binary coded current in response to the lower 10 bits of the digital word to be converted,
The current of bus LNB' is 16 (!l current lit 1 ,
A selected one of '-I 16' is extracted.

Next, a configuration example of the present invention will be shown.

t(a) a plurality of transistors each shouldering a control electrode, an electrode of a constellation 1 coupled to a corresponding one of the current sources, and a second electrode coupled to an output bus;

(b) being coupled to the control electrodes of the plurality of transistors and the bits of the digital word to generate a plurality of control signals, at least one of which corresponds to the plurality of bits, and to cause the selected current source to operate in response to the control signals; means coupled to an output bus through a transistor coupled to the current source, and adapted to couple each selected voltage to the output bus through the same transistor, regardless of the digital word to be converted; selectively electrically coupling or decoupling selected ones of the plurality of current sources to the output bus in accordance with a digital word to generate an output current through the output bus having a level related to the digital word; A digital-to-analog conversion circuit made in 5.

2. (a) A control electrode, a first electrode coupled to a corresponding one of the electrodes am, and an output bus □tL? ,−
jlE2□1□1□o□ ) number of transistors.

(b) a current source coupled to the control electrodes of the plurality of transistors and the bits of the digital word, generating a plurality of control signals, at least one of which is a function of the plurality of bits, and operating in response to the control signals; means for coupling selected ones of said current sources and generating a voltage at the output of said current source to make the voltage generated at the output of each current source independent of said digital word; A selected one of the plurality of current sources is selectively electrically coupled or uncoupled to the output bus in accordance with the digital word to produce an output 11 current through the output bus having a level related to the digital word. Digital-to-analog conversion circuit.

3. (a) combining the bits of a digital word suggestively to generate a plurality of control signals, and making a portion of the control signals correspond to the bits of the digital word Iv! With shout network means.

(b) a plurality of control electrodes each having a control electrode for receiving a corresponding one of the control signals, a first electrode coupled to a corresponding one of the plurality of current sources, and a second electrode coupled to an output bus; a transistor, selectively electrically coupling or uncoupling selected ones of the current sources to the output bus according to the digital word to be converted to provide an output current having a level related to the digital word; A digital-to-analog conversion circuit configured to generate data through a digital-to-analog conversion circuit.

4. (a) At least one of the bits of the digital word
a first plurality of logic gates receiving a first plurality of logic gates and generating a first plurality of output signals representing an AND and complement logic function of the bits of the digital word;

(b) a second plurality of logic gates receiving the first plurality of output signals and generating control signals representing a NOR and 0Rail filling function of the first plurality of output signals; Logic network.

5. (33) a plurality of current sources each having a transistor, each transistor being coupled to a corresponding one of the first plurality of buried gates;

(b) A reference transistor that generates a reference current.

a reference current source having a plurality of transistors of the plurality of current sources matched to the reference transistor and providing a logic threshold signal for the second plurality of logic gates. circuit network.

& each of the first plurality of logic gates includes a reference transistor and at least one input transistor;
The transistor has an emitter electrode coupled to a corresponding one of a plurality of 11H sources, and the logic gate has a first plurality of outputs according to a focus applied to a pace electrode of the at least one input transistor. i number 1
The logic gates each generate one of the collector voltages IIK output logic signal of one of its transistors.
6. The logic circuit network according to item 5, which generates .

-Z The reference current source means includes a reference resistor coupled to the collector electrode of the reference transistor.

7. The logic 31 network of claim 6, wherein said collector electrode provides a logic reference signal for a second plurality of logic gates.

8. The second plurality of gates each include at least one input transistor and a reference transistor, the collector electrodes of the at least one input transistor and the reference transistor are coupled to a control line, and the reference transistor's pace electrode is coupled to a control line. a seventh transistor coupled to the collector electrode of the reference transistor of the current source means, the pace electrode of at least one input transistor of the second plurality of gates being connected to the collector electrode of the first plurality of gates; Logic network described in .

9(a) receiving at least one bit of a digital word and generating a plurality of output signals of Ill;

a first plurality of logic gates, at least a portion of the output signal representing a first discursive combination of the bits, each of the gates comprising a current source;

(bl) a reference voltage +!tIIl matching a current source included in each of the first plurality of logic gates;

(C) means coupled to a reference current source for generating a reference voltage;

(d) receiving the first plurality of output signals and the reference image field to generate a second plurality of output signals representing logical combinations of at least some of the plurality of output signals; and a second plurality of M-filled gates, the plurality of output signals having logic states corresponding to the relative levels of the plurality of output signals and the reference voltage.

10. One of the first and second plurality of logic cases is N
10. The logic circuitry of claim 9, wherein the logic circuitry includes a PNP) register, and the other of the first and second plurality of logic gates includes a PNP) register.

1 t (a3) selectively electrically coupling or uncoupling selected ones of the plurality of constant current sources to the output bus in accordance with the first portion of the digital word in response to the first portion of the digital word; It has a first conversion circuit section, and the conversion circuit section includes (1) a plurality of switching transistors and transistors each having a first electrode coupled to a corresponding one of the plurality of constant current sources.

(1) a plurality of resistor means each coupled between an output bus and a second electrode of a corresponding one of the plurality of switching transistors;

(b) in response to a second portion of said digital word, selectively electrically transmitting a selected one of a plurality of binary current sources to an output bus in accordance with said second portion of said digital word; The plurality of binary current sources have a second conversion circuit section that is coupled or uncoupled.

(1) With multiple current source transistors.

(11) having a resistor disposed at the crossroads, the resistor comprising a resistor ladder network connected to the emitter it pole of the current source transistor;

(C) The resistance values of the plurality of resistors of the first conversion circuit section are such that the W voltage drop occurring across the resistors is converted into the binary voltage across one of the resistors of the branch of the resistor ladder network. 1 is chosen to be equal to the voltage drop produced by one of the current sources.

A digital-to-analog conversion circuit, characterized in that it generates an output current having a level corresponding to the digital word through an output bus.

The preferred embodiments of the present invention have been described above.

It will be apparent to those skilled in the art that other embodiments embodying the technical idea may be used.

Accordingly, the present invention is not limited to the embodiments described above, but rather is limited by the spirit and scope of the claims.

Figure 1 is a schematic connection diagram showing a 12-bit DAC according to the present invention, and Figure 2 is a schematic diagram of the increment logic section used in the DAC of Figure 1. A route connection diagram showing a DAC.

3rd WA is a line connection diagram showing a 12-bit DAC of another embodiment of the present invention, and FIG. 4 is a line connection diagram showing the 12-bit DAC of FIG. 6, including a line connection diagram of an increment logic section used in the DAC. Route connection diagram.

Fig. 5 is a schematic connection diagram showing a 14-pin DAC of another embodiment of the present invention, Fig. 6E is a line connection diagram showing a 14-pin DAC of another embodiment of the invention, and Fig. 7 is DAC in Figure 1
FIG. 8 is a schematic connection diagram showing a part of the resistance ladder network used in FIG.

10... Digital-to-analog conversion circuit (DAC).

14...Reference power supply, 26.26'...I/climent theory 1 buried part・27a~27g'・
・Control line, 28.64...Bus, 30.
30'...R-2R resistance ladder digital-to-analog conversion circuit section, 42...AND-complement logic gate section,
44.44'...0R-NOR gate section, 90~
98...Output line, 200...Master ladder circuit network p 202...Slave ladder circuit network-215
-IC board.

Patent applicant: Raytheon Company (4 others)

Claims (1)

Claims: t (a) Logic circuit for selectively combining a plurality of bits of a digital word to generate a plurality of control signals and causing at least one of the control signals to correspond to a plurality of bits of a digital word. With the net. (bl IN number of constant 1[current sources and; (c) a control electrode receiving a corresponding one of the above control signals; and a first a plurality of transistors each having one electrode and a second electrode coupled to an output bus (dl). A digital-to-analog support circuit characterized in that a current source is selectively electrically coupled to or electrically decoupled from an output bus according to a signal. 2. The plurality of the above. Each of the transistors has a base electrode and a pace electrode, has an emitter electrode as a first electrode, a collector as a second electrode, and each base electrode is coupled to a bus through a resistor. A digital-to-analog conversion circuit according to claim 1.3. A digital-to-analog conversion circuit according to claim 2, wherein the bus is coupled to a reference voltage source.4. (a) Given at least one of the bits of the digital word, the A of the bits of the digital word is
a first plurality of logic gates generating a first plurality of output signals representing ND and complement logic functions; (b) generating a control signal provided with the first plurality of output signals; and a second plurality of logic gates representing NOR and OR logic functions of the plurality of output signals of 1lIJ1. 5. The above logic circuit network is. (a) a plurality of current sources each having a transistor and each coupled to a corresponding one of the first plurality of logic gates; (b) a reference transistor that generates a reference current; and a second plurality of current source transistors matched to the reference transistor. a reference current source means for supplying a logic threshold signal for a second plurality of logic gates; The plurality of logic gates include a reference transistor and at least one input transistor, the transistor having an emitter electrode coupled to a corresponding one of the second plurality of current sources, and each of the salt gates having an emitter electrode coupled to a corresponding one of the second plurality of current sources. one of the first plurality of output logic signals according to the bit provided to the base electrode of the at least one input transistor;
one of the logic gates generates one of the output logic signals at the collector electrode of one of the transistors.
6. A digital-to-analog conversion circuit according to claim 5, wherein the digital-to-analog conversion circuit is configured to generate one of the following. l The reference current source includes a reference resistor coupled to the collector electrode of the reference transistor, the collector electrode providing a logic reference signal for the second plurality of logic gates. Analog conversion circuit. 8. Each of the second plurality of gates includes at least one input transistor and a reference transistor, the at least one input transistor and the reference transistor being coupled to a control electrode of a switching transistor, and a base electrode of the reference transistor being coupled to a current source. a base electrode of at least one input transistor of said second plurality of gates is coupled to a collector electrode of a reference transistor of said means;
8. The digital-to-analog conversion circuit according to claim 7, wherein the digital-to-analog conversion circuit is coupled to collector electrodes of a plurality of gates of.