JPH0432575B2 - - Google Patents

Description

[Detailed description of the invention] (1) Technical field of the invention The present invention is a DAC (Digital-Analog Converter)
In particular, the present invention relates to a function output data converter that outputs a 2 ²ⁿ series.

(2) Technical background DAC is a converter that converts digital signals to analog signals, and is called ADC (Analog-Digital Converter).
At the same time, since information such as physical quantities existing in the natural world is an analog quantity, it is necessary to digitally process these. For this purpose, methods such as addition type, ladder type, resistive voltage division type, etc. are used. A commonly used resistor ladder circuit is also known as R-2R.
This is called a ladder resistance network. This ladder resistance network is a circuit in which resistors R are connected in series in a ladder shape, and one end of resistor 2R is connected between resistors R and R. In addition, resistance 2R
is twice the value of the resistance R. This ladder type resistance circuit includes a constant voltage type, a constant current type, etc. These DACs are mostly ^2N low-grade converters. In addition,
n is a natural number of n = 0, 1, 2, 3, ..., n. For example, in the case of an (R-2R) ladder resistance network, the number of binary bits corresponds to the number of pairs of R, 2R resistors. Then, weighting is performed sequentially.

However, a functional data converter other than the ²ⁿ series, such as a ²²ⁿ series, has not yet been found.

(3) Prior Art and Problems FIG. 1 is a circuit diagram of a conventional 4-bit DAC.

In the figure, the DAC has switches S ₁ ,
..., S ₄ , and one end of this switch is (R-
2R) is connected to the ladder resistor, and the other end is connected to the collector of the transistor in the constant current source circuit.
This ladder resistance network has a ladder configuration of R and 2R. One end of the 2R resistor of this ladder resistor network is connected to ground potential. A voltage -V _EE is applied to the emitter of each transistor via a resistor Re. In addition, the base of each transistor is connected to a reference voltage -
V _REF is applied. Furthermore, this circuit has a configuration compatible with 4 bits.

In the same figure, for example, when switch _S3 is on the ladder resistance side (ON state), if the current flowing through the transistor of the constant current circuit is I, then 2R of the ladder resistance for switch _S3 (1/3) I on the side, (1/3) I on the right R side, R on the left
A current of (1/3)I flows on the side and flows into point _K3 . Therefore, at this time, the output voltage V _OUT becomes (1/3)IR. A similar idea can be applied to points K ₁ , K ₂ , and K ₄ . Therefore, switches S ₁ , S ₂ , S ₃ , and S ₄ are each turned on.
(2/3), (1/2 ³ )IR, (2/3),
(1/2 ² )IR, (2/3), (1/2 ¹ )IR, (2/3), (1/2 ₀ )
IR output voltage can be obtained. In other words, the switches S ₄ , S ₃ , S ₂ , and S ₁ that operate corresponding to each bit of the binary number of the digital signal are weighted with 1/2 ⁰ , 1/2 ¹ , 1/2 ² , and 1/2 ^{3 .} This means that an analog amount of voltage is obtained as an output in accordance with this.

FIG. 2 is a circuit diagram of a conventional 4-bit DAC.

In the figure, an R-2 ladder resistor is connected to the emitter resistor Re of the constant current source circuit transistor in Figure 1, and switches S ₁ ..., S ₄ operate in accordance with each bit of the binary number. One end of the switch is connected to the collector, and the other end of the switch serves as output terminals I _OUT1 and I _OUT2 . The base of each transistor has −V _REF
A potential is applied. Further, -V _EE is added to the connection point between the resistors R and 2R corresponding to the upper bits of the ladder resistance, and -V _REF is added to the base of the transistor. For example, if switch S ₄ is connected to the output I _OUT1 side, and if the current flowing through the transistor is I, then switches S ₃ , S ₂ , and S ₁ are turned ON.
(1/2) for each in the state (entered on the I _OUT1 side)
Currents of I, (1/4)I, and (1/8)I flow. Therefore 8
The weights of (2 ³ ), 4 (2 ² ), 2 (2 ¹ ), and I (2 ⁰ ) are S ₄ and S ₃
，
It is added to S ₂ and S ₁ . This circuit also has the advantage of high impedance when viewed from the output side. Note that predetermined 2 ⁿ series data can be generated by increasing the R-2R ladder resistance corresponding to the number of n in 2 ⁿ .

The two conventional examples shown above express a 2 ⁿ series. Therefore, each circuit had the drawback of not being able to express series other than ²ⁿ .

(4) Object of the Invention An object of the present invention is to provide a function data converter that outputs a 2 ²ⁿ series, unlike the conventional 2 ⁿ series data converter described above.

(5) Structure of the invention This object is to provide a function output data converter that inputs an n-bit digital signal and converts the digital signal into an analog signal, in which (n-1) first resistors are connected in series. A second resistor group having the same resistance value as the first resistor is disposed at both ends of the first resistor group.
One end of each of the (n-2) third resistors having a resistance value twice that of the first resistor is connected to one end of each of the (n-2) resistors connected to each other.
2) connection points, and the other end of each of the (n-2) third resistors is connected to the first power supply together with the other end of each of the second resistors.
-2R ladder resistance network circuit, and the R
- the first in the 2R ladder resistance network
has an output terminal connected to one end of the group of resistors, and has n constant current sources that supply constant current of magnitude I/2 ⁱ (i=0, 1,..., n-1), and A constant current source is connected in descending order of constant current to one end of the first resistor group, (n-2) connection points, and the other end of the first resistor group controlled by the n-bit digital signal. This is achieved by providing a function output data converter, characterized in that the function output data converter is connected through each switch.

(6) Embodiment of the invention Hereinafter, an embodiment of the present invention will be described in detail based on the drawings.

FIG. 3 is a circuit diagram of a functional data converter that outputs a 2 ²ⁿ series according to the present invention. In addition, n
is a natural number.

In the same figure, one embodiment of the present invention has a second resistor Re in the constant current circuit of FIG.
As shown in the figure, it has a configuration in which a (R-2R) ladder resistor is added, and is a 4-bit DAC. Furthermore, these four bits operate current switches S _{1 .} . . , S ₄ corresponding to each bit. _{One of} the switches _{S 1 .} By switching this switch S ₁ ..., S ₄ (R ₁ −2R ₁ )
The current resulting from digital-to-analog conversion by the ladder resistance network is obtained from the output terminal I _OUT2 .

On the other hand, the common terminal of this switch is the transistor
Connected to the collectors of Tr ₁ ..., Tr ₄ . The emitters of these transistors Tr ₁ ..., _Tr4 have (R ₁ −
2R ₁ ) Ladder resistance network is connected. The base of each transistor Tr ₁ ..., Tr ₄ is connected to a reference voltage by Tr ₀ and operational amplifier 1.
V _REF is applied. One end of each 2R ₂ of the (R ₂ −2R ₂ ) ladder resistance network is connected to ground potential, and the R ₁ −2R ₁ ladder resistance network is connected to ground potential.
−V _EE voltage is applied to _one point K′.

In the same figure, current switches S ₁ ..., S ₄ are
The operation when it is on the side that outputs I _OUT2 is as follows, using the ladder resistance network, if the current flowing through Tr ₁ is I, as detailed in Fig. 2 of the conventional example,
The currents flowing between the collector and emitter of each of Tr _{1 .} . . , Tr ₄ are I, (1/2) I, (1/4) I, and (1/8) I. Therefore, for this switch S ₁ ..., S ₄
The converter is weighted by 2 ³ , 2 ² , 2 ¹ , and 2 ⁰ and generates 2 ⁿ series data. This is due to the characteristic of the ladder resistance network that the combined resistance when looking from the upper bit to the lower bit is the same at points K' ₁ ..., K' _4. At the branching point K' ₄ , 2R ₁ , R ₁ Same from the side (1/8)
I, at branch point K' ₃ , 2R ₁ , (1/4) I from R ₁ side, at branch point K' ₂ , 2R ₁ , (1/2) I from R ₁ side, branch point
At K′ ₁ , I flows from the 2R ₁ and R ₁ sides.

Next, when current switch S ₁ ..., S ₄ is on the side that outputs V _OUT1 , the operation is (R ₁ −2R ₁ )
The ladder resistor network and the (R ₂ -2R ₂ ) ladder resistor network perform DAC operations simultaneously. Therefore, the (R ₁ -2R ₁ ) ladder resistance network operates as described above, and the (R ₂ -2R ₂ ) ladder resistance network operates as shown in the conventional example of FIG. Therefore, by combining these two circuit operations, for example, if only current switch _S1 is in the ON state (output V _OUT1 is obtained), a voltage of (1 × 1) 2IR/3 will be applied to the output terminal V _OUT1 . can get. Further, when only the current switch _S2 is in the ON state, a voltage of (1/2×1/2)2IR/3 is obtained at the output terminal _VOUT1 . As described above, when the current switches S ₁ ..., S ₄ are respectively turned on, the output terminal V _OUT1 has (1 x 1) 2IR/3, (1/2 x 1/2) 2IR correspondingly. /3, (1/4×1/4)2IR/3, (1/8×1/8)2IR/3
voltage can be obtained.

Therefore, current switches S ₁ , S ₂ , S ₃ , and S ₄ that are electronically operated by each bit signal (0, 1) have 2 ⁶ (=64), 2 ⁴ (=16), and 2 ² ( =4), 2 ⁰ (=1) weighting is performed. Therefore, the converter according to the embodiment of the present invention can obtain a 2 ²ⁿ series.

Further, according to an embodiment of the present invention, the switch S ₁
..., when _S4 is on the side where the output I _OUT2 is obtained, as mentioned above, the output terminals I _OUT2 have I, (1/2) I, (1/4) with their respective switches in the ON state. I, (1/8)
A current of I flows. Therefore, this is the operation of a commonly encountered binary attenuation type DAC. Therefore,
Current switches S ₁ …, S ₄ can be switched using the output terminals.
Outputs two types of functions: 2 ²ⁿ series obtained at V _OUT1 and 2 ⁿ series obtained at output terminal I _OUT2 .

Alternatively, the resistances of the two ladder resistance networks may be set to R ₁ =R ₂ =R and 2R ₁ =2R ₂ =2R, respectively.

Although one embodiment of the present invention has been described using 4 bits, the number of bits may be increased.

(7) Effects of the Invention As described above in detail, the function output data converter of the present invention is a converter that outputs 2 ²ⁿ series data, which has not been seen before. It is also a converter that can also obtain the conventional ²ⁿ series data mentioned above as output. Therefore, the conventionally obtained 2 ⁿ series data and
It has the advantage of being able to obtain a current output of 2 ²ⁿ series data and being able to perform a variety of processing in a DAC. Further, both the R ₁ -2R ₁ and R ₂ -2R ₂ ladder resistance networks may be R-2R resistance networks.

[Brief explanation of drawings]

Figures 1 and 2 are conventional DAC circuit configuration diagrams,
FIG. 3 is a circuit diagram of the function output data converter of the present invention. Re, R, 2R ₁ , R ₁ , 2R ₂ , R ₂ ...Resistance, S ₁ ,
S ₂ , S ₃ , S ₄ ...Current switch, Tr ₀ , Tr ₁ ,
Tr ₂ , Tr ₃ , Tr ₄ , Tr ₅ ...transistor.

Claims (1)

[Claims] In a function output data converter that inputs a 1 n-bit digital signal and converts the digital signal into an analog signal, the first resistor is formed by connecting (n-1) first resistors in series. One end of a second resistor having the same resistance value as the first resistor is connected to both ends of the first resistor group, and has a resistance value twice that of the first resistor (n
-2) one end of each of the (n-2) third resistors is connected to the (n-2) connection points between the first resistors; an R-2R ladder resistor network circuit whose end is connected to a first power source together with the other end of each of the second resistors, and the first resistor group in the R-2R ladder resistor network circuit has an output terminal connected to one end of the terminal, and has n constant current sources that supply constant currents of magnitude I/2 ⁱ (i=0, 1,..., n-1), and the n constant current sources A source is connected in descending order of constant current to one end of the first resistor group, (n-2) connection points, and the other end of the first resistor group, each controlled by the n-bit digital signal. A function output data converter characterized in that it is connected via a switch. 2 The n constant current sources have (n-1) fourth resistors connected in series, one end of which is connected to a second resistor group, and one end of which is connected to a second power source. A fifth resistor is connected to both ends of the second resistor group and a connection point between the fourth resistors, and each resistor has a resistance value twice that of the fourth resistor, and a reference voltage is connected to the base of the fifth resistor. n first transistors whose emitters are connected to the other ends of each of the fifth resistors and whose collectors are connected to a common terminal of each switch controlled by an n-bit digital signal; , the reference voltage is input to the base, the emitter is connected to the other end of the second resistor group via a sixth resistor having the same resistance value as the fifth resistor, and the collector is connected to the third power supply. 2. The function output data converter according to claim 1, further comprising: a second transistor connected to the function output data converter. 3. The function output data converter according to claim 2, wherein the first resistor and the fourth resistor have equal resistance values.