CA1188810A - Bipolar digital to analog converter - Google Patents
Bipolar digital to analog converterInfo
- Publication number
- CA1188810A CA1188810A CA000412834A CA412834A CA1188810A CA 1188810 A CA1188810 A CA 1188810A CA 000412834 A CA000412834 A CA 000412834A CA 412834 A CA412834 A CA 412834A CA 1188810 A CA1188810 A CA 1188810A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
- H03M1/74—Simultaneous conversion
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Abstract
BIPOLAR DIGITAL TO ANALOG CONVERTER
A bipolar digital to analog converter having a pair of identically configured digital to analog networks, the outputs of which are summed. The input of these networks are connected by an appropriate control circuit which, depending upon whether the digital data is negative or positive, directs the data to one or the other of the networks, to progressively turn that network "on" or "off", depending upon whether the data is increasing or decreasing in its relative value, and which biases the network not receiving the data either completely "off" or completely "on".
A bipolar digital to analog converter having a pair of identically configured digital to analog networks, the outputs of which are summed. The input of these networks are connected by an appropriate control circuit which, depending upon whether the digital data is negative or positive, directs the data to one or the other of the networks, to progressively turn that network "on" or "off", depending upon whether the data is increasing or decreasing in its relative value, and which biases the network not receiving the data either completely "off" or completely "on".
Description
32(),5~6 CAN/RJG
_i BIPOrlAR DIGITAL TO ANALOG CONVERTER
Background of the Invention This invention relates to digital to analog converters and in particular -to bipolar converters having high accuracy at the zero crossover level.
Digital to arialog converters are designed to reconstruct complex and dynamic analog wave ~orms, parti-cularly audio or acoustic signals, from digital data.
When these signals are bipolar, i.e., operating both positively and negatively with respect to a zero cross-over, the complexity required within the converter is greatly increased, usually with a loss in accuracy. In such signals, power occasionally peaks well above the RMS
power level. There mus-t, therefore, be a very large dynamic range to handle the burs-ts of higher arnplitudes, as well as the ability to handle the wide range o~
Erequency interest. Yet, accurately recreating such information from digital data requires exceptional small signal performance to handle the information near zero leveL or crossover without crossover distortion.
In appreciation of this problem, digital to arlalog converters have been devc-loped which separat( the digital input signal into a polarity digit and a number of digits representing the absolute magnitude of the digital ~5 number, i.e., the magnitude excluding the polarity. When this is done, a unipolar digital to analog network can be used to convert the digital signal to i-ts analog equiva-lerlt, and a switchiny or invertiny/non-inverting ampLiEier can be used to restore the polarity to the signal once it has been converted, i.e., depending upon the polarity oE
the input siynal, the output oE the unipolar ciiyital to analoy network is either inverted or non-inverted.
Although this circuit is able ko improve the lineari-ty o~
.small signals in the center region of the Eull scale range, it requires a very accurate and costly inverting amplifier, and therefore tends to remain a limited solution.
~L~`
.3 Another alternative has been to ut:ilize two digital to analog networks, one of which operates from a positive reference source and the other of which operates from a negative reference source. Depending upon the 5 polarity of the input signal as determined by the polarity digit, only one of the digital to analog networks is switched on, with its output being connected to a suitable operational amplifier. In this case only one or the other oE the digital to analog converters i.s used at any given 1~ t.ilne, again to convert the absolute magnitude of the digital data, i.eO, absent the polarity information. This circuit, however, re~uires that a positively operating digital to analog network be matched with a negatively operating digital to analog ne-twork. Since these two 15 digital to analog networks are differently conFigured, it becomes increasingly dificult to find such a matched pair.
Summary of the Present Invention -The bipolar digital to analog converter of the present invention is able to provide relatively accurate 20 conversion at the zero crossover point, as well as at r ~ (Jnitud(~ L(~vc.l.:; w~ oul, 1:1~(' n~ l I~()r .1 I)r(~ ;Ind costly operational amplifier, or matched pairs oE positive and neyative going digital to analog networksO rhis digital to analog converter does not require the digital 25 data to be separated into a portion which corresponds to the absolute magnitude and a portion which corresponds to tl~e ~ol.arity. ~Ithough the polarity or .s~ n i.nForln~ti.on must still be known in order to bias the converter, the converter of the present invention monitors the continu-30 ously changing relative value of the digital signal andproportionately changes its output siynal in response thereto.
The present invention comprises a pair o:E
identically configured digital to analog networks, each 35 having a plurality of input connections for the value digits of the digital data, and an output connection from which an analoy signal corresponding to the digi-tal data can be derived. The output connections of the two networks are electrically connected by an appropriate circuit to sum the outpu-t signals derived -therefrom. The input connec-tions of the two networks are also connected by an appro-priate circuit. This circuit however is responsive to the polarity digit for directing the value digits to one or the other of the digital to analog networks. The circuit also establishes biasing states or biasing conditions for the networks, again in response to the polarity digit. In a first of these states or conditions, the digital ~o analog network not receiving the value digits is biased with a sufficiently high voltage, i.e., a logic "1" condition, to be completely turned on and therefore have a maximum output. The other digital to analog network, i.e., the one receiving data is then turned on or off progressively, as a function of the increase or decrease, respectively, in the relative value of the changing value digits. In a second biasing condition, the digital to analog network not receiving the data is biased with a sufficiently low or logic "0" voltage, to be completely turned off and there-lo~ have a IllinilllUIII or ~ero output. ~he othcr n-twork, i.e., the one receiving the data, is then progressively turned off or on as a function of the decrease or increase, ~cspcctive1y, in the rclativc valuc oE the changin(J valu(?
digits, If it is assumed that the first condition is responding to a sign digit indicating a positive signal and the second condition is responding to a negative signal, the converter of the present invention will have a maximum output for the most positive signal and a minimum of output for the most negative signal. Between these two extremes the output oE the converter will be proportional to the actual value of the digital signal.
Description of the Drawing _ The present invention will be :Eurther described hereinafter with reference to the accompanying drawiny wherein-Figure l is a schematic diagram of the digital to analog converter of the present invention;
Figure 2 is a graph of the transfer character-istics of the converter according to Figure l;
Figure 3 is a circuit diagram of a first embodi-ment of the converter according to Figure l;
Figure 4 is a circuit diagram of a second embodi-snent according to the present invention; and Figure 5 is a circuit diagram of a third embodi-~nent according to the present invention.
Detailed Description The converter lO according to the present invention is schematically illustrated in Figure l. This converter comprises a pair of identically configured digital to analog networks ll and 12 respectively. ~ach of these networks ll or 12 has a plurality of input connections 30 and 31 (represented by a single line), respectively, for digital data, and an output connection 26 and 27, respectively, from which an analog signal corresponding to the digital data can be derived~ The first of these networks ll has its input connections 30 electrically connected to a first circuit 13 which is able to direct either an input source 18 providing a logic "one", or the value digits of the digital data to the network ll. The second digital to analog network 12 is electrically connectéd to second circuit l~ which directs either the value diyits or an input source l9 providing a logic "zerol' to the network 12~ Control means 15, which are responsive to the sign digits of the digital data, determine which of the inputs are directed to the respec-3S tive digital to analog networks 11 and 12. The outputsignals of the two digital to analog networks 11 and 12 are then summed, with the combined output signal being available at terminal 16. As will be discussed, the summing network also contains a terminal 17 at which a DC
bias current can be added to change -the relative DC posi-tion and shape of the resulting output signal. When thecircuits 13 and 1~ are in the first position as indicated in Figurc 1, it can be seen that the ~irst digital to analog network 11 is turned on, i.e. receiving a high level or logic "one" input, and the second digital to analog network 12 is responding to the changes in the value digits~ The maximum output current is therefore ~lowing from the first digital to analog network 11. If the value digits are progressively increasing, the second digital to analog network 12 would respond by progressively increasing its output current until it also is completely turned on, the condition at which the converter 10 would have its maximum output. When the control means 15 switch the source of inputs, the value digits are ~ed to the~
Eirst digital to analog networ~c 11 and a low level or logic "zero" signal is fed to the inputs of the second digital to analog network 12. In this condition, the second digital to analog networlc 12 is turned oE~, ~nd the output current of the first digital to analog network 11 is responding to the changes in the value digits. If it is again assumed that the value digits are progressively increasing, the output current of the networ~c 11 wilL
increase progressively as a function of the increasingly value digits, If the value digits are, however; progres-sively decreasing, the network 11 will be progressiveLy turned off until its output current, and the ou-tput of the converter 10 as well, will he at a minimum value.
Assurning this to be a continuous process with the controller 15 responding to a change in polarity oE
the digital signal, occurring at the time described, the transfer characteristic 20 for the digital to analog converting circuit 10 can be represented as shown in Figure 2. (Note - this graph shows the transfer characteristi.c without the addition of a bias current at terminal 17 as will be discussed.) The abscissa 21 of the graph shown represents the total output current of the converter 10, and the ordinate 22 represents the values of the digital data, separated into the siyn digits 23 and the most significant three bits of the value digits 2~.
It should be noted that for a 12 bi-t converter, which is typical for the present circuit, there would be nine additional value digits (not shown) which form the input to the converter 10. As can be seen from this graph, it is necessary to translate the transfer characteristic 20 to the left by a distance equal to (I out max)/2 in order to make the output current bipolar and equally disposed about the ordinate 22. This can be done by adding a bias current at terminal 17 (see Figure 1). This bias current would be equal in magnitude to one hal~ of the maximum total current which can be produced by the digi-tal to analog networks 11 and 12, but would, however, :Elow in the opposite direction as the output current flowing from the networks. With this addition, the transfer charac~eristic 20 will be translated to the left hy a dis-tance equal to this bias current at terminal 17. The ~ero crossover of the output current would then occur during a -transition oE
the digital input signal between 0 000 and 1 111. ~s can also be seen from this transfer characteristic 20, substan-tially the same output current is present Eor the dlgital values of 0 000 and 1 111. (Note - this situation i.s exaggerated since only the three most siynificant value digits out of the total twelve value digits are shown.) This substantial equality of the current levels exists because at both levels one digital to analog netwo~k is approaching being completely turned on and the other network is approaching being completely turned of:E
(Note - if all digits were shown, an interval would exist where one network would be fully on, and the other fully off). In order to make the transfer characteristic linear .it is necessary to also add a bias current to the output --7~
current of each network 11 and 12 whenever the digital daka is positive, i.e., the sign diyit ~3 is zero. This bias current should be equal in value to the change in output current which occurs for a change in the value oE the least significant digit, i.e., the twelfth diyit. In the pre-ferred embodiment this is done by connecting an appropriate (see Fig. 3) resistor 40 between terminals 41 and ~2.
Whenever the sign digit 23 becomes zero, terminal 41 is high, and a current will Elow through the resistor 40~ The addition of the two bias currents exp]ained above will result in a linear transfer curve which is symmetric about the ordinate 22.
The operation of the present invention is best described by reference to Figure 3 wherein is shown one embGdiment o the digital to analog converter 10. A
commercially available integrated circuit is used Eor each of the networks 11 and 12. This particular integrated circuit has a 12 bit capacity, however, depending upon the degree of accuracy which is required by this digital to naloy converter 10, ot~ler networks havin~ other ~ a~ s are equally viable. For a 12 bit capacity there are twelve inputs 30A through 30L or 31A through 31L. This embodiment also utilizes a plurality of identical integrated circuits for its circuits, designated generally 13 and 1~. Each oE
these integrated circuits is a type SN 74LS157 data selector/multiplexer which is commercially available Erom Texas Instruments, Inc. These data selectors aEford a 4-bit word to be selected from one of two inputs, and routed to a four terrninal output. Thus, Eor a 12-bit digital to analog network, three data selectors must be utilized. The three data selectors ~or the Eirst digitaL
to analog network 11 are designated 32, 33 and 34.
Similarly, the three data selectors Eor the second digital to analog network 12 are designated 35, 36 and 37. As has already been indicated, each oE these data selectors has two sets of four-bit inputs. For the sake of simplicity, the drawing only shows a single line representing the combination of the four-bit inputs. Therefore, in regard to the Eirst data selector 32, the first four bit input is designated 32A and the second four bit input is designated 32B. This same identification scheme is aLso true Eor the re,nainder oE the data selectors. The three data selectors connected to their respective digital to analog networks 11 or 12 are identically configured. Therefore, a description is provided for only the first data selector (i.e. 32 or 35) within each group oE three. This descrip-tion will also apply to the other two data selectors which are connected to that particular digital to analog network 11 or 12.
~ach of the da-ta selectors 32 and 35 contains two addi-tional inputs designated 32C, 32D, and 35C, 35D respec-tively. These two inputs form part of the controller which is utilized to connect the alternative input sources to the corresponding digital to analog network 11 or 12. This particular integrated circuit has a Eunction table which will select the A input when both the C inpu-t and the D
input are low, and select the B input when the C input is low and the D input is high. When the C input is high, the resulting output of the data selectors will be a low voltage or a logic "zero".
The A inputs, i.e. 32A and 35A, are connected to a source which supplies a pre-determined reference vol-tage, and the B inputs, i.e. 32s and 3ss, are the input:!,for the twelve data bits, or value digits which are present in the incoming digital data to being converted.
For the embodi~nent shown in Figure 3, the reEerence voltage at 32A is sufficiently high to bring the network 11 to a logic "one" or on state. Contrastingly, the reference voltage at 35A is sufficiently low, i.e., grounded, to bring the network 12 to a logic "zero" or ofE
state. The third input 32C of the data selectors connected -to the firs-t network 11, is connected to the sign bit or sign digit of the incoming digi-tal data, and the fourth input 32D is grounded, or brought to logic "~ero". For the data selectors connected to the seconcl 'VL~
(ligital to analog network 12, the third input 35C is connected to the inverse of the sign digit of the incoming digital signal, and the fourth input 35D is connected to a voltage source bringing it to a logic i'zero" state.
The logic scheme chosen to encode the digital data, uses a sign digit of zero to indicate a positive signal, and a sign digit of one to indicate a negative signal. Therefore, iE the incoming digital data corresponds to a positive analog signal, the sign bit will be ~ero causing the input 32C to be zero. Since the input 32D is grounded (logic zero), the input 32A will be selected and the input to the Eirst digital to analog network 11 will be logic "ones". The inverse of the zero sign bit is fed to input 35C. Since input 35D is yrounded, the source input 35B is chosen and the digital data is delivered to the second digital to analog network.
12. Alternatively, if the sign bit is one, representing a negative analog signal, input 32C is high and again the input 32D is low. The input 32B is therefore chosen and thc value digits of the digital data arc dclivcrc(l ~o thc first digital to analog network 11~ The input 35C however becomes a logic "zero" due to the inverse o~ the sign bit, resultin~J in a logic "zero" being inputted to the second digital to analog network 12. Thus, Eor positive signals, the first digital to ~nalog network 11 is continuously on and the second digital to analog network 12 is progressive~
ly turned on as a func-tion of the increasing signal value.
lor n~yative signals, however, the seco~ aL tl~
analog network 12 is turned off and the first digital to analog network is progressively turned off as a functiol-ol~ tllc digita:L signal becolning Ino~e ne-~a~ivc. ~s i)a~
already been described, this phenomenon is illustrated by the transfer characteristics shown in Figure 2.
A variation of the present invention is shown in Figure 4. Again ~he same networks 11 and 12, and data selectors 32 throuyh 37 are utilized. As before, -the B
inputs are reserved for the inpu-t of digital data, the 32A
input is connected to a logic "one" reference voltage, input 32C iS connected to the slgn digit, and input 32D is grounded. The A and the C inputs of the second set of data selectors, i.e., 35, 36, and 37, however, are both connected to a reference voltage sufficiently high to be a logic "one", and the sign digit is connected -to the 35D
input. In this configuration a siyn digit of zero will cause 32C to be low. Since 32D iS also low, the 32A input will be chosen and logic "ones" will be Eed to the first network 11. The sign digit will also be connected to input 35D. Hence for a negative signal input 35D will be low. Since input 35C iS always high, the input to the second digital to analog network 12 will be 35B, and the data will be fed to the second digital to analog network 15 12. For a negative signal the sign digit is 1. This results in put 32C being high. Since 32D iS low, input 32B is chosen and the data is fed to the Eirst network 11.
The sign digit of one also causes input 35D to be high.
Since input 35C is also high, logic zeros will be fed to the second network 12. Hence the result is the same as that described for Figure 3.
Although the present inven-tion improves the ability of the digital -to analog networks to convert the zero crossover information, there is still a concern for 25 minor variations which might occur, e.y. even in the ;amc manuEacturing lot of networks, therefore Figure 5 illustrates a third embodiment of the present invention wherein a sisnilar circuit as that already described is shown. The third embodiment, however, contains additional circuitry which effectively serves to toggle or switch the two digital to analog networks 11 and l2 between tl-ei~
respective circuits 13 and l~o This toggling is done at a rate which is approximately one-half the sampling frequency which was originally used to create the digital data Erom its analog equivalent. This toggling of the digital to analog networks 11 and 12 is done to ensure that any discrepency between the two digital to analoy networks 11 ~l 1.--and 12, which might cause error or noise in the analoy siynal, will cause that noise or error at a known frequency, i.e. one-half the sampling frequency. This error or discrepancy can then be Eiltered out. For this 5 ~urpose, a clock pulse is now added at terminal ~5. ~'his clock pulse has a frequency oE one-half -the sampling frequency as described. A configuration of NAND and NOT
gates designated generally 46 form swi-tches which in response to the sign digit and the clock pulse toggle the 10 digital to analog nekworks 11 and 12. The ac-tual condi-tions which are obtained by the gates Eor the various clock and sign bit conditions are indicated in the following table:
Terminal Terminal Terminal ~erminal 15 Clock Sign Bit 50 51 52 53 20 In this embodiment terminal 50 is the 32D input, terminal 51 the 32C input, terminal 52 the 35D input, and terminal 53 the 35C input. Thus for a positive signal the Eirst network 11 toggles between the data and Logic "ol-ec;" whil~
the second network 12 toggles between logic "ones" and the 25 data. For a negative signal, however, the Eirst network 1l tog-Jles between logic "~eros" and data, wh;1e the second network toggles between the data and logic "zeros".
As can be seen, this has the same -transfer characteristic 20, but with the addition of the togglin(3 Eunct;onO
Having thus described several embodiments oE the present invention, it will be understood that changes may be made in the size, shape and configuration oE some oE
the parts or circuits described herein without departing from the present inYention as recited in the appended 35 claims.
_i BIPOrlAR DIGITAL TO ANALOG CONVERTER
Background of the Invention This invention relates to digital to analog converters and in particular -to bipolar converters having high accuracy at the zero crossover level.
Digital to arialog converters are designed to reconstruct complex and dynamic analog wave ~orms, parti-cularly audio or acoustic signals, from digital data.
When these signals are bipolar, i.e., operating both positively and negatively with respect to a zero cross-over, the complexity required within the converter is greatly increased, usually with a loss in accuracy. In such signals, power occasionally peaks well above the RMS
power level. There mus-t, therefore, be a very large dynamic range to handle the burs-ts of higher arnplitudes, as well as the ability to handle the wide range o~
Erequency interest. Yet, accurately recreating such information from digital data requires exceptional small signal performance to handle the information near zero leveL or crossover without crossover distortion.
In appreciation of this problem, digital to arlalog converters have been devc-loped which separat( the digital input signal into a polarity digit and a number of digits representing the absolute magnitude of the digital ~5 number, i.e., the magnitude excluding the polarity. When this is done, a unipolar digital to analog network can be used to convert the digital signal to i-ts analog equiva-lerlt, and a switchiny or invertiny/non-inverting ampLiEier can be used to restore the polarity to the signal once it has been converted, i.e., depending upon the polarity oE
the input siynal, the output oE the unipolar ciiyital to analoy network is either inverted or non-inverted.
Although this circuit is able ko improve the lineari-ty o~
.small signals in the center region of the Eull scale range, it requires a very accurate and costly inverting amplifier, and therefore tends to remain a limited solution.
~L~`
.3 Another alternative has been to ut:ilize two digital to analog networks, one of which operates from a positive reference source and the other of which operates from a negative reference source. Depending upon the 5 polarity of the input signal as determined by the polarity digit, only one of the digital to analog networks is switched on, with its output being connected to a suitable operational amplifier. In this case only one or the other oE the digital to analog converters i.s used at any given 1~ t.ilne, again to convert the absolute magnitude of the digital data, i.eO, absent the polarity information. This circuit, however, re~uires that a positively operating digital to analog network be matched with a negatively operating digital to analog ne-twork. Since these two 15 digital to analog networks are differently conFigured, it becomes increasingly dificult to find such a matched pair.
Summary of the Present Invention -The bipolar digital to analog converter of the present invention is able to provide relatively accurate 20 conversion at the zero crossover point, as well as at r ~ (Jnitud(~ L(~vc.l.:; w~ oul, 1:1~(' n~ l I~()r .1 I)r(~ ;Ind costly operational amplifier, or matched pairs oE positive and neyative going digital to analog networksO rhis digital to analog converter does not require the digital 25 data to be separated into a portion which corresponds to the absolute magnitude and a portion which corresponds to tl~e ~ol.arity. ~Ithough the polarity or .s~ n i.nForln~ti.on must still be known in order to bias the converter, the converter of the present invention monitors the continu-30 ously changing relative value of the digital signal andproportionately changes its output siynal in response thereto.
The present invention comprises a pair o:E
identically configured digital to analog networks, each 35 having a plurality of input connections for the value digits of the digital data, and an output connection from which an analoy signal corresponding to the digi-tal data can be derived. The output connections of the two networks are electrically connected by an appropriate circuit to sum the outpu-t signals derived -therefrom. The input connec-tions of the two networks are also connected by an appro-priate circuit. This circuit however is responsive to the polarity digit for directing the value digits to one or the other of the digital to analog networks. The circuit also establishes biasing states or biasing conditions for the networks, again in response to the polarity digit. In a first of these states or conditions, the digital ~o analog network not receiving the value digits is biased with a sufficiently high voltage, i.e., a logic "1" condition, to be completely turned on and therefore have a maximum output. The other digital to analog network, i.e., the one receiving data is then turned on or off progressively, as a function of the increase or decrease, respectively, in the relative value of the changing value digits. In a second biasing condition, the digital to analog network not receiving the data is biased with a sufficiently low or logic "0" voltage, to be completely turned off and there-lo~ have a IllinilllUIII or ~ero output. ~he othcr n-twork, i.e., the one receiving the data, is then progressively turned off or on as a function of the decrease or increase, ~cspcctive1y, in the rclativc valuc oE the changin(J valu(?
digits, If it is assumed that the first condition is responding to a sign digit indicating a positive signal and the second condition is responding to a negative signal, the converter of the present invention will have a maximum output for the most positive signal and a minimum of output for the most negative signal. Between these two extremes the output oE the converter will be proportional to the actual value of the digital signal.
Description of the Drawing _ The present invention will be :Eurther described hereinafter with reference to the accompanying drawiny wherein-Figure l is a schematic diagram of the digital to analog converter of the present invention;
Figure 2 is a graph of the transfer character-istics of the converter according to Figure l;
Figure 3 is a circuit diagram of a first embodi-ment of the converter according to Figure l;
Figure 4 is a circuit diagram of a second embodi-snent according to the present invention; and Figure 5 is a circuit diagram of a third embodi-~nent according to the present invention.
Detailed Description The converter lO according to the present invention is schematically illustrated in Figure l. This converter comprises a pair of identically configured digital to analog networks ll and 12 respectively. ~ach of these networks ll or 12 has a plurality of input connections 30 and 31 (represented by a single line), respectively, for digital data, and an output connection 26 and 27, respectively, from which an analog signal corresponding to the digital data can be derived~ The first of these networks ll has its input connections 30 electrically connected to a first circuit 13 which is able to direct either an input source 18 providing a logic "one", or the value digits of the digital data to the network ll. The second digital to analog network 12 is electrically connectéd to second circuit l~ which directs either the value diyits or an input source l9 providing a logic "zerol' to the network 12~ Control means 15, which are responsive to the sign digits of the digital data, determine which of the inputs are directed to the respec-3S tive digital to analog networks 11 and 12. The outputsignals of the two digital to analog networks 11 and 12 are then summed, with the combined output signal being available at terminal 16. As will be discussed, the summing network also contains a terminal 17 at which a DC
bias current can be added to change -the relative DC posi-tion and shape of the resulting output signal. When thecircuits 13 and 1~ are in the first position as indicated in Figurc 1, it can be seen that the ~irst digital to analog network 11 is turned on, i.e. receiving a high level or logic "one" input, and the second digital to analog network 12 is responding to the changes in the value digits~ The maximum output current is therefore ~lowing from the first digital to analog network 11. If the value digits are progressively increasing, the second digital to analog network 12 would respond by progressively increasing its output current until it also is completely turned on, the condition at which the converter 10 would have its maximum output. When the control means 15 switch the source of inputs, the value digits are ~ed to the~
Eirst digital to analog networ~c 11 and a low level or logic "zero" signal is fed to the inputs of the second digital to analog network 12. In this condition, the second digital to analog networlc 12 is turned oE~, ~nd the output current of the first digital to analog network 11 is responding to the changes in the value digits. If it is again assumed that the value digits are progressively increasing, the output current of the networ~c 11 wilL
increase progressively as a function of the increasingly value digits, If the value digits are, however; progres-sively decreasing, the network 11 will be progressiveLy turned off until its output current, and the ou-tput of the converter 10 as well, will he at a minimum value.
Assurning this to be a continuous process with the controller 15 responding to a change in polarity oE
the digital signal, occurring at the time described, the transfer characteristic 20 for the digital to analog converting circuit 10 can be represented as shown in Figure 2. (Note - this graph shows the transfer characteristi.c without the addition of a bias current at terminal 17 as will be discussed.) The abscissa 21 of the graph shown represents the total output current of the converter 10, and the ordinate 22 represents the values of the digital data, separated into the siyn digits 23 and the most significant three bits of the value digits 2~.
It should be noted that for a 12 bi-t converter, which is typical for the present circuit, there would be nine additional value digits (not shown) which form the input to the converter 10. As can be seen from this graph, it is necessary to translate the transfer characteristic 20 to the left by a distance equal to (I out max)/2 in order to make the output current bipolar and equally disposed about the ordinate 22. This can be done by adding a bias current at terminal 17 (see Figure 1). This bias current would be equal in magnitude to one hal~ of the maximum total current which can be produced by the digi-tal to analog networks 11 and 12, but would, however, :Elow in the opposite direction as the output current flowing from the networks. With this addition, the transfer charac~eristic 20 will be translated to the left hy a dis-tance equal to this bias current at terminal 17. The ~ero crossover of the output current would then occur during a -transition oE
the digital input signal between 0 000 and 1 111. ~s can also be seen from this transfer characteristic 20, substan-tially the same output current is present Eor the dlgital values of 0 000 and 1 111. (Note - this situation i.s exaggerated since only the three most siynificant value digits out of the total twelve value digits are shown.) This substantial equality of the current levels exists because at both levels one digital to analog netwo~k is approaching being completely turned on and the other network is approaching being completely turned of:E
(Note - if all digits were shown, an interval would exist where one network would be fully on, and the other fully off). In order to make the transfer characteristic linear .it is necessary to also add a bias current to the output --7~
current of each network 11 and 12 whenever the digital daka is positive, i.e., the sign diyit ~3 is zero. This bias current should be equal in value to the change in output current which occurs for a change in the value oE the least significant digit, i.e., the twelfth diyit. In the pre-ferred embodiment this is done by connecting an appropriate (see Fig. 3) resistor 40 between terminals 41 and ~2.
Whenever the sign digit 23 becomes zero, terminal 41 is high, and a current will Elow through the resistor 40~ The addition of the two bias currents exp]ained above will result in a linear transfer curve which is symmetric about the ordinate 22.
The operation of the present invention is best described by reference to Figure 3 wherein is shown one embGdiment o the digital to analog converter 10. A
commercially available integrated circuit is used Eor each of the networks 11 and 12. This particular integrated circuit has a 12 bit capacity, however, depending upon the degree of accuracy which is required by this digital to naloy converter 10, ot~ler networks havin~ other ~ a~ s are equally viable. For a 12 bit capacity there are twelve inputs 30A through 30L or 31A through 31L. This embodiment also utilizes a plurality of identical integrated circuits for its circuits, designated generally 13 and 1~. Each oE
these integrated circuits is a type SN 74LS157 data selector/multiplexer which is commercially available Erom Texas Instruments, Inc. These data selectors aEford a 4-bit word to be selected from one of two inputs, and routed to a four terrninal output. Thus, Eor a 12-bit digital to analog network, three data selectors must be utilized. The three data selectors ~or the Eirst digitaL
to analog network 11 are designated 32, 33 and 34.
Similarly, the three data selectors Eor the second digital to analog network 12 are designated 35, 36 and 37. As has already been indicated, each oE these data selectors has two sets of four-bit inputs. For the sake of simplicity, the drawing only shows a single line representing the combination of the four-bit inputs. Therefore, in regard to the Eirst data selector 32, the first four bit input is designated 32A and the second four bit input is designated 32B. This same identification scheme is aLso true Eor the re,nainder oE the data selectors. The three data selectors connected to their respective digital to analog networks 11 or 12 are identically configured. Therefore, a description is provided for only the first data selector (i.e. 32 or 35) within each group oE three. This descrip-tion will also apply to the other two data selectors which are connected to that particular digital to analog network 11 or 12.
~ach of the da-ta selectors 32 and 35 contains two addi-tional inputs designated 32C, 32D, and 35C, 35D respec-tively. These two inputs form part of the controller which is utilized to connect the alternative input sources to the corresponding digital to analog network 11 or 12. This particular integrated circuit has a Eunction table which will select the A input when both the C inpu-t and the D
input are low, and select the B input when the C input is low and the D input is high. When the C input is high, the resulting output of the data selectors will be a low voltage or a logic "zero".
The A inputs, i.e. 32A and 35A, are connected to a source which supplies a pre-determined reference vol-tage, and the B inputs, i.e. 32s and 3ss, are the input:!,for the twelve data bits, or value digits which are present in the incoming digital data to being converted.
For the embodi~nent shown in Figure 3, the reEerence voltage at 32A is sufficiently high to bring the network 11 to a logic "one" or on state. Contrastingly, the reference voltage at 35A is sufficiently low, i.e., grounded, to bring the network 12 to a logic "zero" or ofE
state. The third input 32C of the data selectors connected -to the firs-t network 11, is connected to the sign bit or sign digit of the incoming digi-tal data, and the fourth input 32D is grounded, or brought to logic "~ero". For the data selectors connected to the seconcl 'VL~
(ligital to analog network 12, the third input 35C is connected to the inverse of the sign digit of the incoming digital signal, and the fourth input 35D is connected to a voltage source bringing it to a logic i'zero" state.
The logic scheme chosen to encode the digital data, uses a sign digit of zero to indicate a positive signal, and a sign digit of one to indicate a negative signal. Therefore, iE the incoming digital data corresponds to a positive analog signal, the sign bit will be ~ero causing the input 32C to be zero. Since the input 32D is grounded (logic zero), the input 32A will be selected and the input to the Eirst digital to analog network 11 will be logic "ones". The inverse of the zero sign bit is fed to input 35C. Since input 35D is yrounded, the source input 35B is chosen and the digital data is delivered to the second digital to analog network.
12. Alternatively, if the sign bit is one, representing a negative analog signal, input 32C is high and again the input 32D is low. The input 32B is therefore chosen and thc value digits of the digital data arc dclivcrc(l ~o thc first digital to analog network 11~ The input 35C however becomes a logic "zero" due to the inverse o~ the sign bit, resultin~J in a logic "zero" being inputted to the second digital to analog network 12. Thus, Eor positive signals, the first digital to ~nalog network 11 is continuously on and the second digital to analog network 12 is progressive~
ly turned on as a func-tion of the increasing signal value.
lor n~yative signals, however, the seco~ aL tl~
analog network 12 is turned off and the first digital to analog network is progressively turned off as a functiol-ol~ tllc digita:L signal becolning Ino~e ne-~a~ivc. ~s i)a~
already been described, this phenomenon is illustrated by the transfer characteristics shown in Figure 2.
A variation of the present invention is shown in Figure 4. Again ~he same networks 11 and 12, and data selectors 32 throuyh 37 are utilized. As before, -the B
inputs are reserved for the inpu-t of digital data, the 32A
input is connected to a logic "one" reference voltage, input 32C iS connected to the slgn digit, and input 32D is grounded. The A and the C inputs of the second set of data selectors, i.e., 35, 36, and 37, however, are both connected to a reference voltage sufficiently high to be a logic "one", and the sign digit is connected -to the 35D
input. In this configuration a siyn digit of zero will cause 32C to be low. Since 32D iS also low, the 32A input will be chosen and logic "ones" will be Eed to the first network 11. The sign digit will also be connected to input 35D. Hence for a negative signal input 35D will be low. Since input 35C iS always high, the input to the second digital to analog network 12 will be 35B, and the data will be fed to the second digital to analog network 15 12. For a negative signal the sign digit is 1. This results in put 32C being high. Since 32D iS low, input 32B is chosen and the data is fed to the Eirst network 11.
The sign digit of one also causes input 35D to be high.
Since input 35C is also high, logic zeros will be fed to the second network 12. Hence the result is the same as that described for Figure 3.
Although the present inven-tion improves the ability of the digital -to analog networks to convert the zero crossover information, there is still a concern for 25 minor variations which might occur, e.y. even in the ;amc manuEacturing lot of networks, therefore Figure 5 illustrates a third embodiment of the present invention wherein a sisnilar circuit as that already described is shown. The third embodiment, however, contains additional circuitry which effectively serves to toggle or switch the two digital to analog networks 11 and l2 between tl-ei~
respective circuits 13 and l~o This toggling is done at a rate which is approximately one-half the sampling frequency which was originally used to create the digital data Erom its analog equivalent. This toggling of the digital to analog networks 11 and 12 is done to ensure that any discrepency between the two digital to analoy networks 11 ~l 1.--and 12, which might cause error or noise in the analoy siynal, will cause that noise or error at a known frequency, i.e. one-half the sampling frequency. This error or discrepancy can then be Eiltered out. For this 5 ~urpose, a clock pulse is now added at terminal ~5. ~'his clock pulse has a frequency oE one-half -the sampling frequency as described. A configuration of NAND and NOT
gates designated generally 46 form swi-tches which in response to the sign digit and the clock pulse toggle the 10 digital to analog nekworks 11 and 12. The ac-tual condi-tions which are obtained by the gates Eor the various clock and sign bit conditions are indicated in the following table:
Terminal Terminal Terminal ~erminal 15 Clock Sign Bit 50 51 52 53 20 In this embodiment terminal 50 is the 32D input, terminal 51 the 32C input, terminal 52 the 35D input, and terminal 53 the 35C input. Thus for a positive signal the Eirst network 11 toggles between the data and Logic "ol-ec;" whil~
the second network 12 toggles between logic "ones" and the 25 data. For a negative signal, however, the Eirst network 1l tog-Jles between logic "~eros" and data, wh;1e the second network toggles between the data and logic "zeros".
As can be seen, this has the same -transfer characteristic 20, but with the addition of the togglin(3 Eunct;onO
Having thus described several embodiments oE the present invention, it will be understood that changes may be made in the size, shape and configuration oE some oE
the parts or circuits described herein without departing from the present inYention as recited in the appended 35 claims.
Claims (7)
1. A digital-to-analog converter for converting bipolar digital data having a series of binary digits including a sign digit and value digits, to its analog equivalent, said converter comprising:
a pair of digital-to-analog networks, each having a plurality of input connections for the value digits of the digital data and an output connection from which an analog signal corresponding to the digital data can be derived;
circuit means responsive to the sign digit and electrically connected to said digital-to-analog networks for directing the value digits to only one of said net-works, and for establishing a first biasing condition for the networks wherein the digital-to-analog network not receiving the value digits is completely turned on and the digital-to-analog network receiving the value digits is turned progressively on or off as a function of the increase or decrease, respectively, in the relative value of the value digits, and for establishing a second biasing condition wherein the digital-to-analog network not receiving the value digits is completely turned off and the digital-to-analog network receiving the value digit is progressively turned off or on as a function of the decrease or increase, respectively, in the relative value of the value digits; and means electrically connected to said output connection of said digital-to-analog networks for summing the output signals, derived therefrom.
a pair of digital-to-analog networks, each having a plurality of input connections for the value digits of the digital data and an output connection from which an analog signal corresponding to the digital data can be derived;
circuit means responsive to the sign digit and electrically connected to said digital-to-analog networks for directing the value digits to only one of said net-works, and for establishing a first biasing condition for the networks wherein the digital-to-analog network not receiving the value digits is completely turned on and the digital-to-analog network receiving the value digits is turned progressively on or off as a function of the increase or decrease, respectively, in the relative value of the value digits, and for establishing a second biasing condition wherein the digital-to-analog network not receiving the value digits is completely turned off and the digital-to-analog network receiving the value digit is progressively turned off or on as a function of the decrease or increase, respectively, in the relative value of the value digits; and means electrically connected to said output connection of said digital-to-analog networks for summing the output signals, derived therefrom.
2. A digital-to-analog converter for converting bipolar digital data having a series of binary digits including a sign digit and value digits, to its analog equivalent, said converter comprising:
a pair of digital-to-analog networks, each having a plurality of input connections for the value digits of the digital data and an output connection from which an analog signal corresponding to the digital data can be derived;
first and second circuits; each comprising a first set of input terminals connected to a reference voltage, a second set of input terminals for the incoming value digits, a set of output terminals connected to said input connections of one of said digital-to-analog networks, means for connecting one of said sets of input terminals to said output terminals, and control means responsive to the sign digit for determining which of the alternative sets of input terminals are connected to said output terminals; and means electrically connected to said output connection of said digital-to-analog networks for summing the output signals derived therefrom.
a pair of digital-to-analog networks, each having a plurality of input connections for the value digits of the digital data and an output connection from which an analog signal corresponding to the digital data can be derived;
first and second circuits; each comprising a first set of input terminals connected to a reference voltage, a second set of input terminals for the incoming value digits, a set of output terminals connected to said input connections of one of said digital-to-analog networks, means for connecting one of said sets of input terminals to said output terminals, and control means responsive to the sign digit for determining which of the alternative sets of input terminals are connected to said output terminals; and means electrically connected to said output connection of said digital-to-analog networks for summing the output signals derived therefrom.
3. A converter as claimed in claim 2 further comprising a terminal at which a DC signal having an opposite polarity to the output signals derived from said digital-to-analog networks can be injected, said terminal being electrically connected to said means for summing the output signals of said digital-to-analog networks.
4. A converter as claimed in claim 3 wherein said reference voltage for said first circuit has suffi-ciently high magnitude to be equivalent to a logic "1" and said reference voltage for said second circuit has suffi-ciently low magnitude to be equivalent to a logic "0".
5. A converter as claimed in claim 3 wherein said reference voltages for said first and said second circuits both have sufficiently high magnitudes to be equivalent to logic "1".
6. A converter as claimed in claim 5 wherein said control means includes two input connections, one of which receives the sign digit, and the other of which is connected to a control reference voltage, said control reference voltage for said first circuit having a sufficiently low magnitude to be equivalent to logic "0"
and said control reference voltage for said second circuit having a sufficiently high magnitude to be equivalent to logic "1".
and said control reference voltage for said second circuit having a sufficiently high magnitude to be equivalent to logic "1".
7. A converter as claimed in claim 2 wherein said circuits include means for connecting said output terminals to a second reference voltage different from said first reference voltage, and said control means includes a timing pulse having a predetermined frequency and means responsive to said timing pulse for activating said means for connecting said output terminals to the second reference voltage.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US320,546 | 1981-11-12 | ||
| US06/320,546 US4473818A (en) | 1981-11-12 | 1981-11-12 | Bipolar digital to analog converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1188810A true CA1188810A (en) | 1985-06-11 |
Family
ID=23246908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000412834A Expired CA1188810A (en) | 1981-11-12 | 1982-10-05 | Bipolar digital to analog converter |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4473818A (en) |
| EP (1) | EP0079681B1 (en) |
| JP (1) | JPS5888923A (en) |
| AU (1) | AU555038B2 (en) |
| CA (1) | CA1188810A (en) |
| DE (1) | DE3280225D1 (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4791405A (en) * | 1986-11-28 | 1988-12-13 | Motorola, Inc. | Data converter for directly providing outputs in two's complement code |
| JPS63256020A (en) * | 1987-04-13 | 1988-10-24 | Matsushita Electric Ind Co Ltd | Digital/analog converter |
| JPH01164125A (en) * | 1987-12-21 | 1989-06-28 | Nissan Motor Co Ltd | D/a conversion circuit |
| US5257027A (en) * | 1992-07-20 | 1993-10-26 | Burr-Brown Corporation | Modified sign-magnitude DAC and method |
| US5689259A (en) * | 1995-07-21 | 1997-11-18 | Exar Corporation | Differental D/A converter with N-bits plus sign |
| US6639534B2 (en) | 2002-02-14 | 2003-10-28 | Silicon Laboratories, Inc. | Digital-to-analog converter switching circuitry |
| CN105850048A (en) * | 2013-08-07 | 2016-08-10 | 艾克泽基因公司 | Precision bipolar current-mode-digital-to-analog converter |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US2878434A (en) * | 1954-05-10 | 1959-03-17 | North American Aviation Inc | Error sensing servo component |
| DE1287622B (en) * | 1964-12-24 | 1969-01-23 | ||
| FR1518697A (en) * | 1966-11-28 | 1968-03-29 | Labo Cent Telecommunicat | Non-linear decoder with discontinuous characteristic |
| US3582939A (en) * | 1969-09-19 | 1971-06-01 | Honeywell Inc | Bipolar digital-to-analog converter |
| US3810157A (en) * | 1972-02-14 | 1974-05-07 | Sperry Rand Corp | Bipolar digital-to-analog converter |
| US3877023A (en) * | 1973-05-21 | 1975-04-08 | Texas Instruments Inc | Antiglitch digital to analog converter system |
| JPS5327353A (en) * | 1976-08-27 | 1978-03-14 | Fujitsu Ltd | Bipolar digital-analog converter |
| FR2449367A1 (en) * | 1979-02-15 | 1980-09-12 | Microsystemes Sarl | A=D signal converter - has weighted outputs of several low resolution converters summed to provide high resolution output |
| US4346368A (en) * | 1979-11-23 | 1982-08-24 | The Boeing Company | Digital-to-analog converter capable of processing a sign magnitude or ones complement binary coded input |
-
1981
- 1981-11-12 US US06/320,546 patent/US4473818A/en not_active Expired - Fee Related
-
1982
- 1982-10-05 CA CA000412834A patent/CA1188810A/en not_active Expired
- 1982-10-13 DE DE8282305443T patent/DE3280225D1/en not_active Expired - Fee Related
- 1982-10-13 EP EP82305443A patent/EP0079681B1/en not_active Expired - Lifetime
- 1982-11-11 AU AU90363/82A patent/AU555038B2/en not_active Ceased
- 1982-11-11 JP JP57196888A patent/JPS5888923A/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| EP0079681B1 (en) | 1990-08-08 |
| EP0079681A3 (en) | 1986-03-19 |
| EP0079681A2 (en) | 1983-05-25 |
| AU555038B2 (en) | 1986-09-11 |
| US4473818A (en) | 1984-09-25 |
| AU9036382A (en) | 1983-05-19 |
| DE3280225D1 (en) | 1990-09-13 |
| JPS5888923A (en) | 1983-05-27 |
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