JP2703120B2 - Digital to analog converter - Google Patents
Digital to analog converterInfo
- Publication number
- JP2703120B2 JP2703120B2 JP2403187A JP40318790A JP2703120B2 JP 2703120 B2 JP2703120 B2 JP 2703120B2 JP 2403187 A JP2403187 A JP 2403187A JP 40318790 A JP40318790 A JP 40318790A JP 2703120 B2 JP2703120 B2 JP 2703120B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- ladder resistor
- ladder
- resistance
- connection point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Analogue/Digital Conversion (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、Ｒ−２Ｒラダー抵抗を
用いたディジタル・アナログ変換器（以下「ＤＡＣ」と
いう。）に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter (hereinafter referred to as "DAC") using an R-2R ladder resistor.
【０００２】[0002]
【従来の技術】従来のＲ−２Ｒラダー抵抗を用いたＤＡ
Ｃ、例えば４ｂｉｔのＤＡＣ１１０においては、図５に
示すようにカレントスイッチ２、３、４、５の差動対１
２、１３、１４、１５を構成する一方のトランジスタ１
２ａ、１３ａ、１４ａ、１５ａのコレクタはＲ−２Ｒラ
ダー抵抗１に接続され、差動対１２、１３、１４、１５
を構成する他方のトランジスタ１２ｂ、１３ｂ、１４
ｂ、１５ｂのコレクタは電源端子Ａに接続されており、
Ｒ−２Ｒラダー抵抗１の電源端子Ａへの配線とトランジ
スタ１２ｂ、１３ｂ、１４ｂ、１５ｂのコレクタの電源
端子Ａへの配線は別々の配線により引き出され、１つの
電源端子Ａに接続されていた。また、各ｂｉｔへの入力
コードは各差動対１２、１３、１４、１５のベースに入
力される。2. Description of the Related Art A DA using a conventional R-2R ladder resistor is used.
C, for example, in a 4-bit DAC 110, the differential pair 1 of the current switches 2, 3, 4, 5 as shown in FIG.
One of transistors 1, 2, 13, 14 and 15
The collectors of 2a, 13a, 14a and 15a are connected to the R-2R ladder resistor 1, and the differential pairs 12, 13, 14, 15
The other transistors 12b, 13b, 14
The collectors of b and 15b are connected to the power supply terminal A,
The wiring to the power supply terminal A of the R-2R ladder resistor 1 and the wiring to the power supply terminal A of the collectors of the transistors 12b, 13b, 14b, and 15b were led out by separate wirings and connected to one power supply terminal A. The input code to each bit is input to the base of each differential pair 12, 13, 14, 15.
【０００３】接点Ａ〜接点Ｂ間の配線長Ｌ1 は、電源端
子の配置によっては数ｍｍ程度になる場合がある。そし
て、接点Ａ〜接点Ｂ間の配線抵抗ＲL1は、配線幅が一定
であるときには配線長Ｌ1 に比例して大きくなることは
一般に知られている。また、接点Ｂ〜接点Ｃ、接点Ｃ〜
接点Ｄ、接点Ｄ〜接点Ｅ間にも同様にＲL2、ＲL3、Ｒ L4
が存在するが、それぞれの配線長、Ｌ2 、Ｌ3 の長さは
数十μｍ程度でＬ1 にに比べ充分に短く、ＲL1》ＲL2Ｒ
L1》ＲL3ＲL1》ＲL4と考えられるので無視できるものと
する。The wiring length L between contacts A and B1Is the power end
It may be several mm depending on the arrangement of the child. Soshi
And the wiring resistance R between the contacts A and BL1Has a fixed wiring width
Is the wiring length L1Can increase in proportion to
Generally known. Also, contact B to contact C, contact C
Contact D, and between contact D and contact E, RL2, RL3, R L4
Exists, but each wiring length, LTwo, LThreeThe length of
L at about tens of μm1Is much shorter thanL1》 RL2R
L1》 RL3RL1》 RL4It can be ignored because it is considered
I do.
【０００４】[0004]
【発明が解決しようとする課題】しかし、この従来例の
ＤＡＣでは、トランジスタ１２ａ、１３ａ、１４ａ、１
５ａのＯＮ、ＯＦＦの状態により接点Ａ〜接点Ｂ間を流
れる電流値が変化し、Ｒ L1の電位降下も同様に変化する
ため、ディジタル入力コードに比例したＤＡＣ出力電圧
が得られず、図６に示すような直線性誤差を示す変換特
性となり、ＤＡＣ出力に悪い影響を与えていた。However, this prior art example
In the DAC, transistors 12a, 13a, 14a, 1
5a flows between the contact points A and B depending on the ON / OFF state of 5a.
Current value changes, R L1Changes in the same way
Therefore, the DAC output voltage is proportional to the digital input code.
Cannot be obtained, and a conversion characteristic indicating a linearity error as shown in FIG.
And adversely affect the DAC output.
【０００５】本発明の目的は、電源配線等の配線抵抗に
よる直線性誤差の少ないＲ−２Ｒラダー抵抗形のディジ
タル・アナログ変換器を提供することにある。It is an object of the present invention to provide an R-2R ladder resistor type digital / analog converter in which a linearity error due to wiring resistance of a power supply wiring or the like is small.
【０００６】[0006]
【課題を解決するための手段】上記課題を解決するため
に、請求項１記載の発明は、第１のＲ−２Ｒラダー抵抗
１と第２のＲ−２Ｒラダー抵抗６を有し、該第１のＲ−
２Ｒラダー抵抗１と該第２のＲ−２Ｒラダー抵抗６のそ
れぞれが、任意の第１の抵抗を有する第１の配線と、該
第１の配線から接続される任意の第２の抵抗を有する第
２の配線と、該第２の配線から接続される任意の第３の
抵抗を有する第３の配線とを有する合成配線を多段に有
し、２番目以降の段においては、前段の合成配線の第１
の配線と、後段の合成配線の第１の配線と第２の配線の
接続点とが接続されると共に、前段の合成配線の第３の
配線と、後段の合成配線の第２の配線と第３の配線の接
続点とが接続されて、最終段においては、最終段の合成
配線の第１の配線と第３の配線とが任意の抵抗を介して
接続され、前記第１のＲ−２Ｒラダー抵抗１の最前段に
おいては、電源端子Ａから最前段の合成配線の第１の配
線と第２の配線の接続点に電源が供給されると共に、該
合成配線の第２の配線と第３の配線の接続点からディジ
タル・アナログ変換出力が出力され、前記第１のＲ−２
Ｒラダー抵抗１と前記第２のＲ−２Ｒラダー抵抗６と
は、多段に接続された合成配線の各々の第１の配線から
構成される電源配線Ａ〜Ｅに関して対称に設けられ、前
記第１のＲ−２Ｒラダー抵抗１の多段に連なる合成配線
の各々の第２の配線と第３の配線の接続点が各々の第１
のトランジスタ１２ａ,１３ａ,１４ａ,１５ａのコレク
タに接続され、前記第２のＲ−２Ｒラダー抵抗６の多段
に連なる合成配線の各々の第２の配線と第３の配線の接
続点が各々の第２のトランジスタ１２ｂ，１３ｂ，１４
ｂ，１５ｂのコレクタに接続されて一対として構成され
る各々の差動対１２，１３，１４，１５を有し、該各々
の差動対１２，１３，１４，１５の共通するエミッタが
各々一の定電流源２２，２３，２４，２５に接続されて
なる各々のカレントスイッチ２，３，４，５を備えるよ
うに構成される。In order to solve the above-mentioned problems, the invention according to claim 1 includes a first R-2R ladder resistor 1 and a second R-2R ladder resistor 6, and the R of 1
Each of the 2R ladder resistor 1 and the second R-2R ladder resistor 6 has a first wiring having an arbitrary first resistance and an arbitrary second resistance connected from the first wiring. In a multi-stage composite wiring having a second wiring and a third wiring having an arbitrary third resistance connected from the second wiring, a composite wiring of a preceding stage is provided in the second and subsequent stages. First
Is connected to the connection point of the first wiring and the second wiring of the subsequent combined wiring, and the third wiring of the preceding combined wiring, the second wiring and the second combined wiring of the subsequent combined wiring are connected to each other. In the final stage, the first wiring and the third wiring of the final stage combined wiring are connected via an arbitrary resistor, and the first R-2R In the forefront stage of the ladder resistor 1, power is supplied from the power supply terminal A to a connection point between the first and second wirings of the foreground combined wiring, and the second and third wirings of the combined wiring are connected to each other. A digital-to-analog conversion output is output from a connection point of the wiring of the first R-2.
The R ladder resistor 1 and the second R-2R ladder resistor 6 are provided symmetrically with respect to power supply wirings A to E each of which is a first wiring of a multi-stage combined wiring, and The connection point between the second wiring and the third wiring of the combined wirings connected in multiple stages of the R-2R ladder resistor 1
Connected to the collectors of the transistors 12a, 13a, 14a, and 15a of the second R-2R ladder resistor 6, and the connection point between the second wiring and the third wiring of the combined wirings connected in multiple stages of the second R-2R ladder resistor 6 2 transistors 12b, 13b, 14
b, 15b, each of which has a pair of differential pairs 12, 13, 14, 15 configured as a pair, and each differential pair 12, 13, 14, 15 has a common emitter. , The current switches 2, 3, 4, and 5 connected to the constant current sources 22, 23, 24, and 25, respectively.
【０００７】[0007]
【０００８】[0008]
【作用】請求項１記載の発明によれば、トランジスタ１
２ａ，１３ａ，１４ａ，１５ａとトランジスタ１２ｂ，
１３ｂ，１４ｂ，１５ｂとが電源配線（Ａ〜Ｅ）から見
て対称に接続されるので、配線抵抗ＲL4，ＲL3，ＲL2，
ＲL1に流れる電流は、トランジスタ１２ａ，１３ａ，１
４ａ，１５ａがオンしたときもトランジスタ１２ｂ，１
３ｂ，１４ｂ，１５ｂがオンしたときも等しい値であ
り、カレントスイッチ２，３，４，５のオン・オフ状態
によって節点Ｄ〜Ｅ，Ｃ〜Ｄ，Ｂ〜Ｃ，Ａ〜Ｂ間の電位
差は変動しない。According to the first aspect of the present invention, the transistor 1
2a, 13a, 14a, 15a and the transistor 12b,
13b, 14b, and 15b are symmetrically connected to the power supply wirings (A to E), so that the wiring resistances R L4 , R L3 , R L2 ,
The current flowing through R L1 is determined by transistors 12a, 13a, 1
When the transistors 4a and 15a are turned on, the transistors 12b and 1
3b, 14b, and 15b have the same value when they are turned on, and the potential difference between the nodes D to E, C to D, B to C, and A to B depends on the on / off state of the current switches 2, 3, 4, and 5. Does not fluctuate.
【０００９】[0009]
【００１０】[0010]
【実施例】次に、本発明の好適な実施例を図面に基づい
て説明する。第１実施例図１に本発明の第１実施例を示
す。図１は、４ｂｉｔのＤＡＣの例を示している。この
ＤＡＣ１００Ａにおいて、カレントスイッチ２、３、
４、５の差動対１２、１３、１４、１５を構成するトラ
ンジスタ１２ａ、１３ａ、１４ａ、１５ａのコレクタは
Ｒ−２Ｒラダー抵抗１に接続され、トランジスタ１２
ｂ、１３ｂ、１４ｂ、１５ｂのコレクタは電源端子端子
ＡとＲ−２Ｒラダー抵抗１側の接点Ｂに接続されてい
る。Next, a preferred embodiment of the present invention will be described with reference to the drawings. First Embodiment FIG. 1 shows a first embodiment of the present invention. FIG. 1 shows an example of a 4-bit DAC. In this DAC 100A, the current switches 2, 3,
The collectors of the transistors 12a, 13a, 14a, and 15a forming the differential pairs 12, 13, 14, 15 of 4, 5 are connected to the R-2R ladder resistor 1, and
The collectors of b, 13b, 14b and 15b are connected to the power supply terminal A and the contact B on the R-2R ladder resistor 1 side.
【００１１】このように、トランジスタ１２ｂ、１３
ｂ、１４ｂ、１５ｂのコレクタを全て接点Ｂに接続する
ことにより、接点Ａ−接点Ｂ間の配線抵抗ＲL1にはＲ−
２Ｒラダー抵抗１に接続されるトランジスタ１２ａ、１
３ａ、１４ａ、１５ａのＯＮ、ＯＦＦの状態によらず電
流値４Ｉの一定電流が流れるため、配線抵抗ＲL1の電位
降下は一定のレベルシフトになり、図４のように直線性
誤差に影響を与えることはない。As described above, the transistors 12b and 13
By connecting all the collectors b, 14b and 15b to the contact B, the wiring resistance R L1 between the contact A and the contact B becomes R-
The transistors 12a, 1a connected to the 2R ladder resistor 1
3a, 14a, 15a ON, and since a constant current flows in the current 4I regardless of the state OFF, the potential drop of the wiring resistance R L1 becomes constant level shift, the influence on the linearity error as in FIG. 4 I will not give.
【００１２】第２実施例次に、図２に本発明の第２実施
例を示す。図２は４ｂｉｔのＤＡＣの例を示している。
このＤＡＣ１００Ｂと第１実施例のＤＡＣ１００Ａとの
違いは、トランジスタ１２ｂ、１３ｂ、１４ｂ、１５ｂ
のコレクタをＲ−２Ｒラダー抵抗１の接点Ｂ、Ｃ、Ｄ、
Ｅにそれぞれ接続していることである。この場合も接点
Ａ〜接点Ｂ間の電流はトランジスタ１２ａ、１３ａ、１
４ａ、１５ａのＯＮ、ＯＦＦの状態によらず一定とな
り、配線抵抗ＲL1の電位降下による直線性誤差の影響を
キャンセルすることができる。また図５の従来例の説明
では無視できるとしたＲL2、ＲL3、ＲL4の影響も減少さ
せることができる。 Second Embodiment Next, FIG. 2 shows a second embodiment of the present invention. FIG. 2 shows an example of a 4-bit DAC.
The difference between the DAC 100B and the DAC 100A of the first embodiment is that the transistors 12b, 13b, 14b, 15b
Are connected to the contacts B, C, D, of the R-2R ladder resistor 1.
E respectively. Also in this case, the current between the contact A and the contact B is the transistor 12a, 13a, 1
It becomes constant irrespective of the ON / OFF state of 4a and 15a, and the effect of the linearity error due to the potential drop of the wiring resistance RL1 can be canceled. In addition, the effects of R L2 , R L3 , and R L4 which can be ignored in the description of the conventional example of FIG. 5 can be reduced.
【００１３】各ｂｉｔが０１１１から１０００（０：ト
ランジスタ１２ａ〜１５ａがＯＦＦ、１：トランジスタ
１２ａ〜１５ａがＯＮ）に変化する時の接点Ａ〜接点Ｂ
間、接点Ｂ〜接点Ｃ間、接点Ｃ〜接点Ｄ間、接点Ｄ〜接
点Ｅ間に流れる電流の変化を第１実施例と第２実施例と
についてまとめたものが表１、表２である。表１、表２
からわかるように、第２実施例では、第１実施例に比
べ、ＲL2、ＲL3、ＲL4に流れる電流の変化が小さくなっ
ている。Contacts A and B when each bit changes from 0111 to 1000 (0: transistors 12a to 15a are off, 1: transistors 12a to 15a are on)
Tables 1 and 2 summarize changes in the current flowing between the contacts B and C, between the contacts C and D, and between the contacts D and E for the first embodiment and the second embodiment. . Table 1, Table 2
As can be seen from the graph, in the second embodiment, the change in the current flowing through R L2 , R L3 , and R L4 is smaller than in the first embodiment.
【００１４】[0014]
【表１】 [Table 1]
【００１５】[0015]
【表２】 [Table 2]
【００１６】第３実施例次に、図３に本発明の第３実施
例を示す。図３は４ｂｉｔのＤＡＣの例を示している。
このＤＡＣ１００Ｃでは、トランジスタ１２ｂ、１３
ｂ、１４ｂ、１５ｂのコレクタを他のＲ−２Ｒラダー抵
抗６を通してそれぞれ接点Ｂ、Ｃ、Ｄ、Ｅに接続する。
これにより接点Ａ〜接点Ｂ間の配線抵抗ＲL1の他に接点
Ｂ〜接点Ｃ、接点Ｃ〜接点Ｄ、接点Ｄ〜接点Ｅ間の配線
抵抗ＲL2、ＲL3、ＲL4にも各ｂｉｔの論理に関係なく一
定電流が流れるため、接点Ａ〜Ｅ間の配線抵抗による直
線性誤差の影響を全てキャンセルすることができる。 Third Embodiment Next, FIG. 3 shows a third embodiment of the present invention. FIG. 3 shows an example of a 4-bit DAC.
In the DAC 100C, the transistors 12b and 13
The collectors of b, 14b and 15b are connected to the contacts B, C, D and E through other R-2R ladder resistors 6, respectively.
Thus in addition to the contact B~ contact C of the wiring resistance R L1 between the contacts A~ contacts B, contact C~ contacts D, also the wiring resistance R L2, R L3, R L4 between the contact points D~ contact E of each bit Since a constant current flows irrespective of the logic, all the effects of the linearity error due to the wiring resistance between the contacts A to E can be canceled.
【００１７】この第３実施例ではＲL1、ＲL2、ＲL3、Ｒ
L4の影響を完全にキャンセルすることができるが、新た
に他のＲ−２Ｒラダー抵抗６を追加する必要がある。一
方、第２実施例では、従来例の電源配線の接続を変更す
るのみでＲL1の影響をキャンセルし、ＲL2、ＲL3、ＲL4
の影響を小さく抑えることができるという違いがある。In the third embodiment, R L1 , R L2 , R L3 , R
Although the influence of L4 can be completely canceled, another R-2R ladder resistor 6 needs to be newly added. On the other hand, in the second embodiment, it cancels only the influence of R L1 to change the connection of a conventional example of a power supply wiring, R L2, R L3, R L4
There is a difference in that the effect of can be kept small.
【００１８】[0018]
【発明の効果】以上説明したように、本発明によれば、
Ｒ−２Ｒラダー抵抗を用いるＤＡＣにおいてＲ−２Ｒラ
ダー抵抗から電源端子への配線の配線抵抗による直線性
誤差を無くすことができ、ＤＡＣの性能向上に寄与しう
るという利点を有する。As described above, according to the present invention,
In a DAC using an R-2R ladder resistor, there is an advantage that a linearity error due to the wiring resistance of the wiring from the R-2R ladder resistor to the power supply terminal can be eliminated, which can contribute to the performance improvement of the DAC.
【図１】本発明の第１実施例の構成を示す図である。FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.
【図２】本発明の第２実施例の構成を示す図である。FIG. 2 is a diagram showing a configuration of a second exemplary embodiment of the present invention.
【図３】本発明の第３実施例の構成を示す図である。FIG. 3 is a diagram showing a configuration of a third embodiment of the present invention.
【図４】本発明の第１実施例のＤ／Ａ変換特性を示す図
である。FIG. 4 is a diagram showing D / A conversion characteristics of the first embodiment of the present invention.
【図５】従来例のディジタル・アナログ変換器の構成を
示す図である。FIG. 5 is a diagram showing a configuration of a conventional digital-to-analog converter.
【図６】従来例のディジタル・アナログ変換器のＤ／Ａ
変換特性を示す図である。FIG. 6 shows a D / A of a conventional digital / analog converter.
FIG. 4 is a diagram illustrating conversion characteristics.
１…Ｒ−２Ｒラダー抵抗２、３、４、５…カレントスイ
ッチ１２、１３、１４、１５…差動対１２ａ、１３ａ、
１４ａ、１５ａ…トランジスタ１２ｂ、１３ｂ、１４
ｂ、１５ｂ…トランジスタ２２、２、２４、２５…定電
流源１００Ａ、１００Ｂ、１００Ｃ、１１０…ディジタ
ル・アナログ変換器Ａ…電源端子Ｂ、Ｃ、Ｄ、Ｅ…接点
Ｆ…ＤＡＣ出力端子Ｌ1 、Ｌ2 、Ｌ3 、Ｌ4 …配線長Ｒ
…抵抗ＲL1、ＲL2、ＲL3、ＲL4…配線抵抗1 ... R-2R ladder resistor 2,3,4,5 ... current switch 12,13,14,15 ... differential pair 12a, 13a,
14a, 15a ... transistors 12b, 13b, 14
b, 15b transistors 22, 2, 24, 25 constant current sources 100A, 100B, 100C, 110 digital-to-analog converter A power terminals B, C, D, E contacts F DAC output terminals L 1 , L 2 , L 3 , L 4 ... wiring length R
… Resistance RL1 , RL2 , RL3 , RL4 … Wiring resistance
Claims (1)
のＲ−２Ｒラダー抵抗（６）を有し、該第１のＲ−２Ｒ
ラダー抵抗（１）と該第２のＲ−２Ｒラダー抵抗（６）
のそれぞれが、任意の第１の抵抗を有する第１の配線
と、該第１の配線から接続される任意の第２の抵抗を有
する第２の配線と、該第２の配線から接続される任意の
第３の抵抗を有する第３の配線とを有する合成配線を多
段に有し、２番目以降の段においては、前段の合成配線
の第１の配線と、後段の合成配線の第１の配線と第２の
配線の接続点とが接続されると共に、前段の合成配線の
第３の配線と、後段の合成配線の第２の配線と第３の配
線の接続点とが接続されて、最終段においては、最終段
の合成配線の第１の配線と第３の配線とが任意の抵抗を
介して接続され、 前記第１のＲ−２Ｒラダー抵抗（１）の最前段において
は、電源端子（Ａ）から最前段の合成配線の第１の配線
と第２の配線の接続点に電源が供給されると共に、該合
成配線の第２の配線と第３の配線の接続点からディジタ
ル・アナログ変換出力が出力され、 前記第１のＲ−２Ｒラダー抵抗（１）と前記第２のＲ−
２Ｒラダー抵抗（６）とは、多段に接続された合成配線
の各々の第１の配線から構成される電源配線（Ａ〜Ｅ）
に関して対称に設けられ、 前記第１のＲ−２Ｒラダー抵抗（１）の多段に連なる合
成配線の各々の第２の配線と第３の配線の接続点が各々
の第１のトランジスタ（１２ａ,１３ａ,１４ａ,１５
ａ）のコレクタに接続され、前記第２のＲ−２Ｒラダー
抵抗（６）の多段に連なる合成配線の各々の第２の配線
と第３の配線の接続点が各々の第２のトランジスタ（１
２ｂ，１３ｂ，１４ｂ，１５ｂ）のコレクタに接続され
て一対として構成される各々の差動対（１２，１３，１
４，１５）を有し、該各々の差動対（１２，１３，１
４，１５）の共通するエミッタが各々一の定電流源（２
２，２３，２４，２５）に接続されてなる各々のカレン
トスイッチ（２，３，４，５）を備えた、 ことを特徴とするディジタル・アナログ変換器。A first R-2R ladder resistor and a second R-2R ladder resistor;
R-2R ladder resistor (6), and the first R-2R
Ladder resistance (1) and the second R-2R ladder resistance (6)
Each have an arbitrary first resistance
And an arbitrary second resistor connected from the first wiring.
A second wiring to be connected, and an arbitrary
A large number of composite wirings including the third wiring having the third resistance are provided.
For the second and subsequent stages, the composite wiring of the previous stage
Of the composite wiring of the subsequent stage and the second wiring
The connection point of the wiring is connected, and the
A third wiring, and a second wiring and a third wiring of the subsequent composite wiring.
The connection point of the line is connected, and in the final stage, the final stage
The first and third wirings of the composite wiring of FIG.
At the forefront of the first R-2R ladder resistor (1).
Is the first wiring of the first-stage combined wiring from the power supply terminal (A)
Power is supplied to the connection point between the
Digital is connected from the connection point between the second wiring and the third wiring of the formed wiring.
Le analog conversion output is output, the first R-2R ladder resistor (1) and the second R-
2R ladder resistor (6) is a composite wiring connected in multiple stages
Power supply wirings (A to E) composed of respective first wirings
And the multi-stage combination of the first R-2R ladder resistor (1) is provided.
The connection point of each of the second wiring and the third wiring of the formed wiring is
Of the first transistors (12a, 13a, 14a, 15
a) the second R-2R ladder connected to the collector of
Second wiring of each of multi-stage combined wirings of resistance (6)
The connection point of the third wiring and each of the second transistors (1
2b, 13b, 14b, 15b)
Each differential pair (12, 13, 1
4,15), and each differential pair (12,13,1)
4, 15) are connected to one constant current source (2
2, 23, 24, 25)
A digital-to-analog converter, comprising a digital switch (2, 3, 4, 5) .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2403187A JP2703120B2 (en) | 1990-12-18 | 1990-12-18 | Digital to analog converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2403187A JP2703120B2 (en) | 1990-12-18 | 1990-12-18 | Digital to analog converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04217120A JPH04217120A (en) | 1992-08-07 |
| JP2703120B2 true JP2703120B2 (en) | 1998-01-26 |
Family
ID=18512943
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2403187A Expired - Lifetime JP2703120B2 (en) | 1990-12-18 | 1990-12-18 | Digital to analog converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2703120B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5706008A (en) * | 1996-03-01 | 1998-01-06 | Analog Devices, Inc. | High bandwidth parallel analog-to-digital converter |
| JP3169884B2 (en) * | 1998-02-26 | 2001-05-28 | 日本電気アイシーマイコンシステム株式会社 | Digital-to-analog converter and test method therefor |
| JP2010074015A (en) | 2008-09-22 | 2010-04-02 | Hitachi Ltd | Semiconductor device |
| EP4170911A1 (en) | 2021-10-20 | 2023-04-26 | Socionext Inc. | Differential circuitry |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4521765A (en) * | 1981-04-03 | 1985-06-04 | Burr-Brown Corporation | Circuit and method for reducing non-linearity in analog output current due to waste current switching |
-
1990
- 1990-12-18 JP JP2403187A patent/JP2703120B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04217120A (en) | 1992-08-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19970909 |