JPS58114423A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58114423A JPS58114423A JP21086281A JP21086281A JPS58114423A JP S58114423 A JPS58114423 A JP S58114423A JP 21086281 A JP21086281 A JP 21086281A JP 21086281 A JP21086281 A JP 21086281A JP S58114423 A JPS58114423 A JP S58114423A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- interface
- film
- electrode
- compound semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 150000001875 compounds Chemical class 0.000 claims abstract description 16
- 239000002344 surface layer Substances 0.000 claims abstract description 10
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims abstract description 7
- 239000001257 hydrogen Substances 0.000 claims abstract description 6
- 229910052739 hydrogen Inorganic materials 0.000 claims abstract description 6
- 230000001681 protective effect Effects 0.000 claims description 17
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 14
- 239000010410 layer Substances 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 12
- 229910052751 metal Inorganic materials 0.000 abstract description 6
- 239000002184 metal Substances 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 230000008030 elimination Effects 0.000 abstract description 2
- 238000003379 elimination reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910017083 AlN Inorganic materials 0.000 abstract 1
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 238000010438 heat treatment Methods 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000002411 adverse Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Substances [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910052779 Neodymium Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 235000021018 plums Nutrition 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
Abstract
Description
【発明の詳細な説明】
（→ 発明の技術分野
本発明は化合物半導体を用いた半導体装置の製造法、特
に化合物半導体の表面に形成される表面準位を該化合物
半導体で形成する素子の特性に悪影響を及ぼすことなく
除去する熱処理方法を提供するものであるみ
程中に容易に表一単位が形成されて素子特性に悪影響を
及ぼす、例えば低周波雑音の増大や素子諸特性が時間と
共に変動するドリア）現象等が生ずる。これらの表明単
位は表面保護膜を形成した後にも完全に取り来ることが
できずに素子製作後にも残る。[Detailed Description of the Invention] (→ Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a compound semiconductor, and in particular to a method for manufacturing a semiconductor device using a compound semiconductor, and in particular, a method of manufacturing a semiconductor device using a compound semiconductor, and in particular, a method for manufacturing a semiconductor device using a compound semiconductor. This provides a heat treatment method that removes these units without causing any adverse effects.Table 1 units are easily formed during processing and have an adverse effect on device characteristics, such as an increase in low frequency noise and changes in device characteristics over time. Doria) phenomenon etc. occur. These expression units cannot be completely removed even after the surface protective film is formed and remain even after the device is fabricated.
（→ 従来技術と問題点
以下にはガリュウム砒素電界効果トランジスタ（Ｇａム
＃ＩＦ］ＩＩＴ）を例に用いて説明する。(→ Prior Art and Problems) The following description uses a gallium arsenide field effect transistor (GaM #IF] IIT) as an example.
＊ｔＷｌは牛絶縁性ＱａＡｚ基板１の上層に％型のへか
のエピタキシャル層２を形成した化合物半導体基板上に
形成した電界効果Ｆランジスタ（Ｆｌ！Ｔ）の断面模式
間で、８はソース電極、４はショットキー接合を有する
ゲート電極、５はドレイン電極６は表面保護膜である。*tWl is a schematic cross-sectional diagram of a field effect F transistor (Fl!T) formed on a compound semiconductor substrate with a % type heka epitaxial layer 2 formed on top of an insulating QaAz substrate 1, and 8 is a source electrode. , 4 is a gate electrode having a Schottky junction, and 5 is a drain electrode 6 which is a surface protective film.
以上のような構成のＦＦ１Ｔの電極はアルミニウム（ム
ｌ）や（Ａｓ）−白金（Ｐｔ）−チタン（Ｔ（）の積層
構造を有しており、表ｒｔ’Ｏｉ
面保護膜にはｈ喬＊ ８ｉ１ Ｎ４ ｅムｊＮ、Ｐ２Ｏ
等の絶縁膜が気相化学沈積法（ＯＶＤ）や蒸着法にて付
着されている。The electrode of FF1T with the above structure has a laminated structure of aluminum (Mul) or (As)-platinum (Pt)-titanium (T()), and the surface protective film is * 8i1 N4 emujN, P2O
Insulating films such as these are deposited by vapor phase chemical deposition (OVD) or vapor deposition.
ところが表面層Ｓ膜６の形成下、すなわち、ソースとゲ
ート電極間、およびゲートとドレイン電極間部分にＧｇ
Ａｚの０６がぬけだし、ルが過剰になった表面準位が形
成され、その結果点４Ｉ＠で示すような空乏層が形成さ
れる。この結果ゲー）の容量はゲート空乏層容量ＣＩに
ソースとゲート間およびゲートとドレイン間の表面保護
下の界面準位によって発生した空乏層容量０ｚｅＯｏが
並列に入った形となる。However, under the formation of the surface layer S film 6, that is, between the source and gate electrodes and between the gate and drain electrodes, Gg
06 of Az leaks out, and a surface level with excess Ru is formed, resulting in the formation of a depletion layer as shown at point 4I@. As a result, the capacitance of the capacitor (G) is the gate depletion layer capacitance CI and the depletion layer capacitance 0zeOo generated by the interface state between the source and the gate and between the gate and the drain under surface protection, which is in parallel.
結局ゲート空乏層容量はＧｌ÷Ｃ＃◆ＣＤとなり高周波
特性は大幅に低下する。従って、上記の表面準位によっ
て生ずる不要な容量Ｏｌおよび偽を無くするには、水素
ガス（烏）雰囲気中で約６００℃の温度で熱処理すれば
、Ｇ＠ＡＪ基板の表面層近傍に存在していた前記の過剰
な砒素（ム＃）が鵬と反応して、アルシン（ムＪＨＰ
）となり昇華する。このように熱処理を施せば表面単位
を無くすることはできるが、ゲー）４にアルミニウムを
用いた場合、アルミニウム（五ｌ）がＧｇ＆中へ浸透し
アロイ化して、ゲートのショツＦキー特性を劣化し、初
期の素子特性を得ることができない。In the end, the gate depletion layer capacitance becomes Gl÷C#◆CD, and the high frequency characteristics are significantly degraded. Therefore, in order to eliminate the unnecessary capacitance Ol and false caused by the above-mentioned surface states, heat treatment at a temperature of approximately 600°C in a hydrogen gas atmosphere will eliminate the unnecessary capacitance Ol and the false capacitance that exist near the surface layer of the G@AJ substrate. The excess arsenic (mu#) that was present reacts with the
) and sublimate. If heat treatment is performed in this way, surface units can be eliminated, but if aluminum is used for Gg&4, aluminum (5L) will penetrate into Gg& and form an alloy, deteriorating the short F key characteristics of the gate. However, initial device characteristics cannot be obtained.
（→ 発明の目的
本発明は、前起表面保麺膜直下の不要な表面単位に起因
する空乏層をなくシ、シかもゲージ金属であるアルミニ
ウム（Ａｔ＞とガリウム砒素エピタキシャル層２との間
のシロットキー接合特性が破壊されない熱処理法を提供
するものである〇（−） 発明の構成
この発明は、水素雰囲気中で、化合物半導体上に形成し
た表面保護膜を通して該化合物半導体の表面層をレーザ
光で照射することによって、表面保護膜下の該化合物半
導体の表面層を熱処理することを特徴とするもので、ア
ルミ電極等の金属電極部は加熱することなく良好な特性
の半導体素子を製造する半導体装置の製造方法を提供す
る。(→ Purpose of the Invention The present invention aims to eliminate the depletion layer caused by unnecessary surface units directly under the pre-raised surface noodle-retaining film. This invention provides a heat treatment method that does not destroy Sirot-Key junction characteristics. 〇 (-) Structure of the Invention This invention provides a method for treating the surface layer of a compound semiconductor with a laser beam through a surface protective film formed on the compound semiconductor in a hydrogen atmosphere. A semiconductor device characterized in that the surface layer of the compound semiconductor under the surface protective film is heat-treated by irradiation, and a semiconductor element with good characteristics is manufactured without heating the metal electrode part such as an aluminum electrode. Provides a manufacturing method.
ω 発明の実施例
以下本発明をＧａＡＪＦ］ｅＴの実施例について第２図
を用いて詳細に説明する。なお図において第１図と同一
符号は同一機能を示す◎
本発明の熱処理法としての熱源には表面保護膜１ｉｓ疏
として用いる絶縁材料である８ ４０＠ ｅ番−一陶、
ム４鴇Ｐ、８．Ｇ等を透過し、ゲージ金属４であるＭ等
によっては完全反射し、しかも基板であるＧｅＡｚでは
吸収されるＧ６ムＩのバンドギャップより炸い、波長が
５０００人〜８５００人程度のレーザ光を用いる。ω Embodiments of the Invention The present invention will be described in detail below with reference to FIG. 2 regarding an embodiment of GaAJF]eT. In the figures, the same symbols as in Figure 1 indicate the same functions. ◎ The heat source for the heat treatment method of the present invention is an insulating material used as a surface protective film 1.
Mu 4 Toki P, 8. It transmits G, etc., is completely reflected by M, etc., which is gauge metal 4, and is absorbed by GeAz, which is the substrate. use
なお本奥−例においてＧａＡＪのエピタキシャル層２の
厚みは０．８５−程度であり、表面層護膜６としては、
厚さがｙｏｏｏλ程度の８ｉｏ！をＯＶＤ法で設けたも
のである。またアニール用のレーザ光源としてはアルゴ
ン（ムｒ）ガスレーザやネオジエウムヤグＣＮｄ−Ｙム
Ｇ）レーザを用いる。これらのレーザ光はパルス幅数１
０ＩｋＩ′Ｃ１１ｔＨ力数ワツトのものを用いるとよく
、このようなレーザ光Ｐを第２図に示すような素子を形
成した基板を水素雰囲気中に設置し、基板の表面から掃
引するか、各素子が間欠的に照射されるようにする。こ
のよりなレーザ光Ｐの照射時間は例えばＧｇｓム、ＦＩ
Ｔの場合数１０−照射する。これによって表面保護膜６
の直下Ｇａ４基板のみが加熱され、前記表面保護膜６と
エピタキシャル層２との界面に形成されていた過剰の９
ｚ
が雰囲気中の梅と反応してアルシン（ム＃Ｂｓ）を形成
し、表面保議膜６を通して逃げ出し、その結果表面単位
を無くすることができる。一方ゲート４金属等であるム
ｔの表面を照射したレーザ光は反射され、ムｌや、その
直下のＧｇＡＪ基板な加熱しないため、ゲート金属であ
るムｌとＧｇＡＪとがア田イ（合金）化せず、従来の熱
処理法のような素子特性の劣化を生じない。In addition, in the Motooku example, the thickness of the GaAJ epitaxial layer 2 is about 0.85 mm, and the surface layer protective film 6 is as follows:
8io with a thickness of about yoooλ! was provided using the OVD method. Further, as a laser light source for annealing, an argon (Mr) gas laser or a neodymium (YAG) laser is used. These laser beams have a pulse width of 1
A laser beam P with a power of 0IkI'C11tH in watts is preferably used. A substrate on which elements as shown in FIG. 2 are formed is placed in a hydrogen atmosphere, and the laser beam P is swept from the surface of the substrate or is irradiated intermittently. The irradiation time of this sharp laser beam P is, for example, Ggsm, FI
For T, the number 10 is irradiated. As a result, the surface protective film 6
Only the Ga4 substrate immediately below is heated, and the excess 9 formed at the interface between the surface protective film 6 and the epitaxial layer 2 is heated.
z reacts with plums in the atmosphere to form arsine (Mu#Bs), which escapes through the surface retention film 6, resulting in the elimination of surface units. On the other hand, the laser beam irradiated on the surface of the gate 4 metal, etc., is reflected and does not heat the gate metal or the GgAJ substrate directly under it. This method does not cause deterioration of device characteristics unlike conventional heat treatment methods.
結局レーザ光の照射によって温度が上昇するのはソース
とゲート間及びゲートとドレイン間に形成したＢｉａｓ
表面保表面摸下の界面だけである０ゲートとＧ６ムｌ結
晶界面は、ゲートの両側の表面層護膜の部分から、わず
かに熱伝導によって加熱されるだけであり、レーザ光の
照射時間を調整することにより、表面層１！＠の直下の
界面のＧｇＡｚ結晶の表面のみを瞬時に所要の温度であ
る６００℃近傍に高めることができる。After all, the temperature rises due to laser light irradiation because of the bias formed between the source and gate and between the gate and drain.
The 0 gate and G6 ml crystal interface, which is only the interface under the surface protective surface, is only slightly heated by thermal conduction from the surface protective film on both sides of the gate, and the laser beam irradiation time is By adjusting the surface layer 1! Only the surface of the GgAz crystal at the interface directly below @ can be instantly raised to the required temperature of around 600°C.
ＣＩ＞ 発明の効果
以上詳細に説明したように化合物半導体の表面に表面保
護膜を形成した基板を水素雰囲気中に設置し、表面保護
膜は透過し、化合物半導体では吸収され、電極金属では
反射するレーザ光を用いて基板上に形成した表面保護膜
の上側から走査または間欠的に照射することによって、
化合物半導体基板と表面保護膜との界面の不純物単位を
除去することができ、表面保護膜と化合物半導体基板と
の界面に生ずる不要な容量を除去することができ素子の
特性を劣化することなく高層波特性を改善することがで
きる。CI> Effects of the Invention As explained in detail above, a substrate with a surface protective film formed on the surface of a compound semiconductor is placed in a hydrogen atmosphere, and the hydrogen is transmitted through the surface protective film, absorbed by the compound semiconductor, and reflected by the electrode metal. By scanning or intermittently irradiating the surface protective film formed on the substrate with laser light,
Impurity units at the interface between the compound semiconductor substrate and the surface protection film can be removed, and unnecessary capacitance generated at the interface between the surface protection film and the compound semiconductor substrate can be removed. Wave characteristics can be improved.
なお以上の１ｍ２明ではＧａムＩを用いたＦＩＴを例に
説明したが、他の化金物半導体を用いた素子製作工程に
レーザ光を用いたアニール法を採用することによって、
同様の素子特性の改善を行うことができる。In addition, in the above 1m2 light, FIT using Ga-I was explained as an example, but by adopting an annealing method using laser light in the device manufacturing process using other metal compound semiconductors,
Similar improvements in device characteristics can be made.
第１図は熱処理を施さないＧ６ム＃ＩＦＩＩＩ＋の特性
を説明する図、ｌＩＩ！図は本発明を用いたＧ６ム、
ＦＩＴの素子製作工程を説明する図である。
ｌは半絶縁性０６ムＩ基板、２はエピタキシャル成長法
にて形成したＧｇＡＪ素子形成領域、８はソース電極、
４はゲート電極、６はドレイン電極、６は表面保護膜、
ｒはレーザ光である。
第１１！１
第２ｒＭFigure 1 is a diagram explaining the characteristics of G6 mu #IFIII+ without heat treatment, lII! The figure shows a G6 system using the present invention.
It is a figure explaining the element manufacturing process of FIT. 1 is a semi-insulating 06μI substrate, 2 is a GgAJ element formation region formed by epitaxial growth, 8 is a source electrode,
4 is a gate electrode, 6 is a drain electrode, 6 is a surface protective film,
r is a laser beam. 11th!1st 2nd rM
Claims (1)
を通して該化合物半導体の表面層をレーザ光で照射する
ことによって、表面保護膜下の該化合物半導体の表面層
を熱処理することを特徴とする半導体装置の製造方法。A semiconductor characterized in that the surface layer of the compound semiconductor under the surface protective film is heat-treated by irradiating the surface layer of the compound semiconductor with laser light through the surface protective film formed on the compound semiconductor in a hydrogen atmosphere. Method of manufacturing the device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21086281A JPS58114423A (en) | 1981-12-28 | 1981-12-28 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21086281A JPS58114423A (en) | 1981-12-28 | 1981-12-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58114423A true JPS58114423A (en) | 1983-07-07 |
Family
ID=16596327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21086281A Pending JPS58114423A (en) | 1981-12-28 | 1981-12-28 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58114423A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61260625A (en) * | 1985-05-15 | 1986-11-18 | Sony Corp | Reforming for interface of insulator layer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623748A (en) * | 1979-08-05 | 1981-03-06 | Shunpei Yamazaki | Manufacture of semiconductor device |
-
1981
- 1981-12-28 JP JP21086281A patent/JPS58114423A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5623748A (en) * | 1979-08-05 | 1981-03-06 | Shunpei Yamazaki | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61260625A (en) * | 1985-05-15 | 1986-11-18 | Sony Corp | Reforming for interface of insulator layer |
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