JPS58114258A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the amount of hardware, by making an arrangement that the contents of an external storage means which can write but cannot read out, can be read out from another external storage means which can write and read out. CONSTITUTION:When a microprocessor MPU10 accesses RAMs 11 and 12 or read-only registes 15-1-15-2, the contents of the registers 15-1-15-2 are sent to the MPU10 by the selecting operation of a multiplexer MPX16. When a writing operation is performed in write-only registers 13-1-13-2, an address value is sent from the MPU10. Therefore, the writing data from the MPU10 is written in an assigned register of the registers 13-1-13-2 and, at the same time, the data is also written in an assigned address position in an register area 18 of the RAM12. Accordingly, when the MPU10 reads the write-only registers 13-1-13-2, data of the same contents are obtained by performing the read-out access to the register area 18 of the RAM12.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention 1I11 relates to a data processing device K, in particular, a processing device, an external storage means capable of both writing and reading from a line processing device, and a wrinkle processing device. The present invention relates to a data processing device including other external storage means that can only be written to and cannot be read from an m device.

(2) Technical background Although the present invention is not limited thereto, for example, when configuring a data processing device using a microprocessor as the processing device, it is important to reduce the amount of hardware from the viewpoint of economicalization. This is considered an issue. Microprocessors normally use external registers, which are interfaces with surrounding logic circuits, to proceed with processing, but the number of these external registers increases as the number of external logic circuits increases. It continues to increase. The scale of the multi-register means for reading St out of these external registers from the microprocessor also increases.

(3) Conventional technology and study point #! FIG. 1 shows a general configuration example of a data processing device using a microprocessor. In the figure, IF1 is a microprocessor MPU, 2 and 3 are random access memory RAMs that can be read/written, 912 is a program area, 3 is a data area, and 4t! Register A
, 5 is a logic circuit, 6 is a register B, and 7t; t multiplexer MPX.

In FIG. 1, RAM2, RAM3, register A4゜register 86% are microprocessor MP
These are used as external storage means for the UI, especially RAM3, register A4. Register B6% is treated as a data area. Here, regarding the RAM 3, even if its capacity increases in the address direction, the configuration of the multiplexer 7 does not change, but regarding the write/continue register (register A4, register area, etc.),
As the number increases, the scale of the multiplexer 7 becomes larger and the amount of hardware thereof increases. Therefore, in order to reduce the amount of hardware in the multiplexer 7, it may be possible to dedicate it to writing to the illustrated register A4'i, but in this case, the disadvantage is that it becomes impossible to determine the content written to the wrinkle register A4. occurs. One way to solve this problem is to write data 't111F into register A4 after microprocessor t1 writes:
Although it is conceivable to save the same data in another RAM 3%, this method has the disadvantage that the processing capacity of the microprocessor 1 is reduced.

(4) Purpose of the Invention The present invention solves the above problems and provides a data processing device that makes it possible to reduce the amount of hardware required without reducing the processing capacity of a processing device such as a microprocessor. (5) Structure of the Invention In order to achieve the above object, the present invention provides a processing device, an external storage means capable of both writing and data writing from the processing device, and In a data processing device that includes another external storage means that can only be written to and cannot be read, a part of the address of the external storage means that can be written to and read from cannot be read. By matching the address of the external storage means with the address of the external storage means, the contents of the other external storage means that can only be written to but cannot be read can be successively retrieved from the external storage means that can be written to and read from both. is % mold.

(6) Embodiment of the invention Fig. 2 is a block diagram of a data processing device according to an embodiment by Akira Motokaji, in which 10 is a microphone d processor MPU;
lit'i Random access memory RAM capable of both reading and writing and having a siprogram area, 12
It is a random access memory RAM that can be read/written continuously and has register area 18 and data area 192.
13-1 to 13-2 are convolution-only registers, 14 is a logic circuit, 15-1 to 15-2 are read-only registers, 16 is a multiplexer MPX, and 17 is a quality checker.0 Rattan 3 The figure is a diagram showing the address structure g (memory map) of external storage in the data processing device of the embodiment. As is clear from figure 0, addresses θ to (A
-1) area is in the data area of RAM12 at address A.
~ Address (B-1) is register area 18 of RAM 12
and register A in common from address B to address (C
-1) are respectively assigned to register B. The operation of the embodiment is as follows: O microprocessor 10
When accessing RAM II from the microprocessor IO, the value of the address D is sent from the microprocessor IO and the access is performed. Also, when the microprocessor 10 accesses the data area 19 of the RAM 12, the microprocessor 10 sends out the value of address θ~(A-1) and the access is delayed.On the other hand, when accessing the register, , read-only register 15
-1 to 15-2 are accessed (setting operation), the microprocessor 10 sends out the values of address B to address (C-1). 15-1 to 15-
The contents of a predetermined register among the two are sent to the microprocessor 10. Next, the capital dedicated register 13-1
When a write operation to 13-2 is performed, the values of addresses A to (B-1) are sent from the microgross processor 10. ), microprocessor 10
The write data sent from registers 13-1 to 1
It is written (set) into the designated register of 3-2, and is also written into the designated address position tic41 of the register area 18 of the RAM 12.

Shut up! When the microprocessor 10 wants to read the contents of the write-only registers 13-1 to 13-2,
By performing a read access to the register area 18 of the RAM 12, it is possible to obtain data with the same contents as the contents of the corresponding register. set bit (SETBIT) command or reset pin) to control
(RESET BIT) Instruction t - Frequently used.

These instructions read the contents of a register, perform arithmetic operations on the microprocessor, and fold it into the corresponding register, but in order to execute these instructions quickly, it is necessary to read the contents of the register quickly. . According to the invention,
The performance of processing these instructions will not be degraded. Furthermore, since parity is usually added to random access memory RAM and read-only memory ROM without adding parity to external registers, it is necessary to judge whether or not to perform a parity check. However, according to the present invention, a parity check is always performed when reading data from RAM, so that when reading access to registers 13-1 to 13-2, there is no need to judge whether it is a RAM or a register. The advantage is that it is simplified.

Although the above embodiment uses a microprocessor as the processing device, it is not limited to the data processing device using the microprocessor of the present invention, and it is obvious that it can be applied to any other Natsupro Nanatsusa. It is.

(7) Effects of the Invention According to the present invention, the amount of hardware surrounding the processing device can be reduced without deteriorating the performance of the processing device, and the cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a general configuration example of a data processing device using a Fii microprocessor, FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG. 3 is a diagram showing a memory map in the embodiment. In FIG. 2, 10F1 microprocessor, 11 and 12F1 random access memory, 13-1 to 13-2
is a write-only register, 15-1 to 15-2 are read-only registers, and 16 is a multiplexer.

Claims (1)

[Claims] In a data processing device, the data processing device includes a processing device, an external storage device capable of both writing and reading from the processing device, and another external storage device that can only be stored and cannot be read from the line processing device, By making a part of the address of the external storage means capable of both writing and reading coincide with the address of the other external storage means capable of only writing but not allowing reading, the above-mentioned writing only possible and reading can be performed. 1. A data processing IMl device characterized in that the contents of other external storage means in which data cannot be written can be retrieved from the external storage means that can be written and read.