JPS58112142A - Program processor - Google Patents

Abstract

PURPOSE:To facilitate a change for a part of a program within an ROM, by comparing the address of a program under execution with a set address to be changed and then selecting a memory with the output of comparison. CONSTITUTION:An address comparator 101 compares the address of a program under execution which is given by the output of an address sequence controlling circuit 3 with the address of data to be changed which is given from an address switch 1. Then a coincidence signal is delivered when the coincidence is obtained from the comparison. Receiving this coincidence signal, a selecting circuit containing an NOR gate 108 and an OR gate 109 switches a working program memory 4 to a subprogram memory 5. As a result, the contents written previously in the memory 5 can be executed only for a program to which a change is desired in the memory 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an i-microgram type processor, for example, a processor used as a control device in a high-speed input/output control device, an image processing device, etc. The present invention relates to a program processing device that processes operations of a program memory provided in a processor.

Technical Background of the Invention: A processor is usually equipped with a program memory. The configuration of such a program memory can be broadly classified into the following three types. One is RAM (, Ran-aom A
(IQ@l@Memory), the trick is to use ROM (Read Only Memory).
y), the three K are ROM and RAM.
The present invention relates to the first and third configuration, that is, a program memory configured using a combination of 1'tOM and RAM. In such a program memory configuration (8-), ROM is mainly used and KRAM is used as an auxiliary one. Therefore, ROM is the main program memory (or seventh program memory), and RM is the subprogram memory. (or second program memory). However, in this specification, in order to simplify the explanation, they will be simply abbreviated as ROM and RM.

FIG. 1 is a block diagram showing an example of a processor equipped with the above-mentioned ROM and RAM combined program memory. 1st
In the figure, an address switch 1 is used to specify an address when starting a program from an arbitrary address, or as a writing device for writing data into RAMj, which will be described later. Therefore, this address switch 1 is mainly used in depacking programs.

The address selector is for selecting one of the address field from the instruction register 6 and the set address from the address switch 1, which will be described later. This address selector normally selects the address field side, and selects the address value during adjustment or depacking.

The address sequence control circuit 3 has a control function for sending an address signal to each element in response to an address signal received via an address selector.

ROM# is 5, so to speak, the main program memory,
As mentioned earlier, fixed program data is stored.

The RAMj is a so-called subprogram memory, and arbitrary data is written to an arbitrary address by manual operation of the address switch l. Since the storage capacity is used as an auxiliary to ROMj, it may be smaller than that of ROMj.

Instruction register t is ROM≠ or RAM
It has a latch function in part to output the instruction of the data stored in j, and the output signal causes the ROM4! Alternatively, various commands in RAMj are executed.

The branch command decode circuit 7 detects an unconditional or conditional jump or subroutine call command from among the instructions given from the instruction register 4. The output signal is sent to the address sequence control circuit JK and used to determine the address of the program to be executed first.

The clock control circuit t generates a predetermined clock pulse (address/instruction latch clock) and supplies it to the address sequence circuit J and the instruction register 4.

The memory selection circuit de includes a select switch 10 and an input/output switch 10.
When writing data to RAMj or executing a program using the contents of RAMj, the select switch IO is closed.
AMj operates and ROM4I stops.

That is, when the select switch 10 is open, ROMp is selected, and when it is closed, RAMj is selected.

FIG. 3 shows the processing operation timing of the above processor. One cycle of the address/instruction latch clock OK from the clock control/control circuit 1 is 7.
This is a command cycle, and in this cycle Address Muku R1
The operand OPL is provided, and each Yuzu command is executed sequentially by pipeline summation.

Problems in the Background Art In a processor equipped with a combined program memory of ROM and RAM, if a 'bug' is found as a result of program depacking or adjustment, Vr needs to change the data content of the 1 bug' part. There is.

However, in the case of ROM, the data is already fixed, so in order to change the data contents, the ROM must be replaced each time. Furthermore, especially when the contents of the ROM are temporarily changed for adjustment, replacing the ROM each time results in a huge loss in terms of time and cost.

Purpose of the Invention Therefore, the present invention provides R at each time of depacking and adjustment.
It is an object of the present invention to provide a program processing device in which a part of a program in a ROM can be easily changed without the need to replace the OM.

Summary of the Invention The present invention is characterized by setting the address of data desired to be changed in a first program memory (ROM), and storing the changed data at an arbitrary address in the first program memory (RAM). Compares the address of the program currently being executed with the set change address, and both addresses match [7 and water - address comparison to output new signal] and a memory selection circuit that outputs a selection signal for switching the operating memory from the first program memory to the second program memory in response to the above-mentioned new signal, When the program progresses to address K of the change data, the program memory is truncated from the first program memory to the first program memory, and only the program that needs to be changed is written in advance to the fourth program memory. It is busy executing the contents and then enabling the contents of the first program memory to be executed again.

Examples of the invention Hereinafter, the present invention will be clearly described based on illustrative embodiments.

[Configuration] The configuration of the program processing device according to the present invention is shown in FIG. 3. The parts that differ between the configuration in FIG. 3 and the configuration in FIG. Since the other parts are the same, the same reference numerals are given and the explanation thereof will be omitted.

In FIG. 3, the address comparison circuit 10/ compares the address of the currently executing program given by the output of the address sequence control circuit J and the address of the modified data (address of ROM reference) given by the address switch 1. Comparison is performed, and when both addresses match, the match signal ADREQ that is output is logical % / #
becomes.

The 10 address-scattering output circuits each have a gate switch 10 that opens and closes depending on whether or not the program memory is switched.
J, I/Putter 10 that inverts its output signal, and a match signal MDR'BQ, and invert! 1011 output is used as input to calculate the AND of the coincidence signal DRIIIQ.
Goo) 101 and MMD Goo) 101 output and address I/stock switch lock clock OK are input, match signal I) RIQ is set to logic %/#, and message switching signal MO is output. It is composed of an R-87 lip-flop/It.

Memory selection circuit @ 107 includes the circuit shown in Fig. 1, as well as the NO.
R gate 10r and OR gate 10? It is composed of This memory selection circuit 107 outputs a memory switching signal MO on the condition that the select switch 10 is open.
is logical %11, the operating memory is changed from ROM4t to R
A selection signal am, which switches to AM, l.

Outputs 8m. When Era is logic 10#, RAM
When j is activated and S- is logical %11, ROM4C is activated.

[Operation] Next, the operation of the circuit shown in FIG. 3 will be explained.

Figure 4 is a diagram explaining the relationship between ROM4I and RAMj. Here, the capacity of ROM$ is taken as lOJ reference word, and R
Let the capacity of AMj be Jj4 words. Now, for example, when depacking, etc., I want to change the content OD of the program at address 10 (2 + overdisplay) in ROMJ, so I manually write the new data MD I want to change to address oto in RAMj using the address switch. Next, the address switch 1 is set to address 2to, the gate switch 103 of the address-integration output circuit 102 is closed, and the select switch 1/ of the memory selection circuit 107 is left open.

The program in ROM4I is started in the above state.

When the 11th program progresses and the address ADH output from the address sequence control circuit J reaches address 110, the input conditions of the address comparison circuit 10/ match, so the address comparison circuit 10/ outputs a match signal AD! tl
Outputs Q (logic '/'). At this time, the umbrella switch lO3 is closed, so the output logic of the inverter 1101d is 57'. Therefore, ANI) Gate I
The output logic of the output is also %/I, which is applied to the set input terminal of the 7 lip-flop tot. Therefore, the output of the Aritz flop 104, that is, the switching signal MO is also 'l
'. Then, in the memory selection circuit 107, the output of the MOR gate/Dr becomes % g jF, and the output of the OR gate 10 becomes 'l'. ROM4Q stops, and RAMj starts operating. The starting address of RAMj is address 0IO as shown in FIG. That is, the memory to be operated here is the one given from the ROM to the ROM jK switching register and the instruction register t! RAMj
This changes to the data stored at address 0tO, and this is the instruction/regine! This will become the operand OPL and be executed.

When the execution of the contents of the oro address of RAMj is completed, the address ADH given to the address comparison circuit/DIK no longer satisfies the input condition, and as a result, the memory is reloaded to the RO address.
Return to M≠. Below, the program stored in RO)JJ will be executed.

In the above operation, the set clock for 10 flip-flops, some signals, DRIQ, switching signal MO1, .
' Figure 3 shows the tie 2/g of the eight selected signal towns.

Effects of the Invention As described above, according to the present invention, the data to be changed in the first program memory can be written by the writing device. By setting the address of the change program and writing new data to replace the change data in advance to an arbitrary address of the second coprogram memory, when the execution program reaches the address of the change program that has been set, the address comparison circuit A match signal is issued, and based on a part of the signal, the memory selection circuit switches the operating memory from the first program memory to the first program memory.Therefore, only for programs that require change in the first program memory. It becomes possible to execute the contents written in advance in the first coprogram memory. As a result, when depacking etc., RO
It is not necessary to replace the first program memory composed of M each time, and it is possible to provide a program processing installation that can easily change a part of the contents in the first program memory.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional processor, FIG. 2 is a time chart for explaining the operation of signals of each part of the conventional processor, and FIG. 3 is a block diagram of a processor including an embodiment of a program processing device according to the present invention. Figure 1 is an explanatory diagram of the program contents of the ROM and RAM, and Figure 1 is for explaining the operation of the signals of each part of the program processing device according to the present invention. Im chart. l...address switch, l...first program content (ROM), j...first program memory (
RAM), 10/...address comparison circuit, lOco...
-Address-scattering output circuit, 107...Memory selection circuit.

Claims (1)

[Scope of Claims] In a processor comprising a first program memory that is not writable and a second program memory that is writable, an address of modified data in the first program memory is set; and a writing device for writing new data in place of the changed data to an arbitrary address in the third program memory, and a comparison between the address of the program being executed and the address of the set budding data I. an address comparison circuit that outputs a match signal when both addresses match; and a memory selection circuit that receives the match signal and outputs a selection signal that switches the operating memory from the first program memory to the second program memory. A program processing device comprising: