JPH01169629A - Rom patching system - Google Patents

Abstract

PURPOSE:To realize the change of a program without stopping a system and without preparing a new ROM by executing the program changed in a RAM while continuing the access action of the ROM due to the ROM access source. CONSTITUTION:When a program after the change to cope with the continuous condition can be prepared, the program after the change is stored into a RAM 13. The storing of the change program and the setting action of an address are executed during the action of the system, and in the access action from a ROM access source 10 after the setting, the address supplied to the address bus is coincident with the access set at a setting address detecting means 11, and then, a coincident output is given to a switching control means 14. The switching control means 14 executes the switching control, the action of a ROM 12 is prohibited by a control signal 141, the RAM 13 is operated by a control signal 142, and the program after the change in the RAM 13 is executed. Thus, when the program is to be changed, the program by the change contents can be executed without preparing the new ROM and without stopping the system.

Description

[Detailed Description of the Invention] [Summary] Regarding the ROM patch method for partially changing the contents of the ROM in an information processing system in which programs are stored in the ROM, it is necessary to use a new The purpose of this invention is to provide a ROM patching method for an information processing system that enables the execution of a program based on the changed contents without creating a new ROM and without stopping the system immediately after the changed contents are determined. In an information processing system in which a ROM is connected to a ROM access source by a bus, the R, OM
a set address detection means for detecting that an address at which a program in the program is to be changed is set and a set address is generated on the bus; a RAM connected to the bus that stores the changed program; and a set address detection means for detecting the set address. A switching control means is provided for supplying a prohibition signal to the ROM and a control signal to the RAM in response to the generation of the output, and a switching control means for supplying a prohibition signal to the ROM and a control signal to the RAM.
Configure to run the modified program in .

"Field of Industrial Application" The present invention relates to a ROM patch method for partially changing the contents of a ROM in an information processing system in which a program is stored in a ROM.

In addition, "Patch (Patch) J" in the name of the present invention
is used in the same sense as patch (clothing), patch plate, etc.

In information processing system technology, control programs such as O8 (operating system) and various application programs are stored in auxiliary storage devices such as magnetic disks and transferred to RAM (random access) when the system is started up or when needed. However, in the case of small-scale information processing systems used in terminals, it is not affected by the environment of the installation location, and it is easy to process at startup (power supply Software (O8 works immediately when turned on) etc.
(including control programs and application programs) may be stored in a ROM (read-only memory).

When you first install and test an information processing system that uses such ROM as main memory (of course a small working RAM is included), or when an error occurs during operation after installation, the program (including tables) There are times when you want to change a part of the information processing system, but traditionally this was handled by stopping the operation of the information processing system and replacing the original ROM with a ROM with new contents created elsewhere. It took a lot of time and effort, and a more efficient method was desired.

[Prior Art] An example of an information processing system equipped with a ROM that stores a control program (O8) and an application program is a terminal device system that is located away from a central computer. The device is connected to the central computer through a communication path, and executes processes such as inputting (or collecting) information around the terminal, transmitting it to the central computer, and outputting data sent from the central computer, using a program.

When an information processing system used as such a terminal device is installed, an on-site operation test is conducted to check whether it operates as planned. Furthermore, when an error occurs, it is common practice to observe the situation on-site and investigate the cause.

As a result of tests and investigations by engineers, it may be determined that the ROM will work better if the program is changed, or
In some cases, it may be possible to assume that the problem can be solved by changing the numerical values in the ROM table.

Conventionally, in cases like this, to change even one bit of ROM data, create a new ROM and replace the old ROM.
It is necessary to replace it with .

In other words, since this cannot be done at the installation site, we go back to the ROM manufacturing site, create a ROM using a ROM writer, etc. with the modified program, assemble a system that reproduces the situation, perform an operation test, and confirm that it works well. At that time, I followed the procedure of replacing the original old ROM with a new ROM.

According to the method described in Section 2 of ``Problems to be Solved by the Invention,'' it is necessary to create a new ROM in order to partially change the contents of the ROM, which takes time and effort, and the service is interrupted during that time. There are times when you have to stop (when there is a bald spot in the program). Also, even if the service is not stopped until the new ROM is completed, RO
There were problems such as the need to stop the system when replacing M with a new one.

The present invention makes it possible to execute a program according to the changed contents without having to create a new ROM when a part of the program (data) in the ROM is desired to be changed, and without stopping the system immediately after the changed contents are determined. The purpose of this paper is to provide a ROM patch method for information processing systems.

[Means for solving problems] The basic configuration of the present invention is shown in FIG.

In FIG. 1, 10 is a ROM access source, 11 is a set address detection means, 12 is a ROM, 13 is a RAM, and 14 is a
101 represents a switching control means, 101 represents an address bus, and 102 represents a data bus.

The RAM 13 stores a program after changing the program to be changed in the ROM 12, and the address of the ROM 12 in which the program to be changed is stored is set in the set address detection means 11.

In the present invention, the address of the program to be changed in the ROM 12 is set in the setting address detection means 11, and in the read operation by the ROM access source 10, the address supplied to the address bus is determined by the setting address detection means 11, and the setting address is set. When an address is detected, switching control means 1
4 to prohibit the reading operation from the ROM 12 and read the changed program from the RAM 13.

[Function] When the ROM access operation 0 supplies an address to the address bus 101 to read a program, the program (including tables) data stored at the corresponding address in the ROM 12 is normally read out and transferred to the data bus. 102, and the output of this data bus is stored in the ROM.
The access source 10 performs receiving and receiving processing.

When executing information processing using the ROM 12, if an error occurs or a need arises to perform control appropriate to the situation at that time, and you are able to create a modified program to deal with it, , stores the modified program in the RAM 13.

At the same time, the address of the ROM 12 in which the program to be changed is stored is set in the setting address detection means 11.

This change program storage and address setting operation is performed while the system is operating, and after the setting, ROM access #i10
In the access operation from , when the address supplied to the address bus matches the address set in the set address detection means 11 , a -match output is given to the switching control means 14 .

The switching control means 14 performs switching control, prohibits the operation of the ROM 12 using the control signal 141, and generates a control signal using the control signal 142 to control the operation of the RAM 1.
3 and execute the modified program in the RAM 13.

[Embodiment 1.2 of the embodiment configuration of the present invention is shown in FIGS. 2 and 3.

First, a first example configuration will be explained using FIG. 2.

20 in FIG. 2 is a central processing unit (represented by CPU), 21 is a console, 22 is a setting address register, 23 is a comparison circuit, 24 is a ROM, and 25 is a RAM.

The information processing system shown in FIG. 2 includes, for example, various devices (
It is used as a terminal device (equipped with an input/output device (not shown)) that has the function of collecting data representing the output status of measuring devices, control devices, etc.) and outputting control data to those devices. It can be connected to a central computer system via.

To explain the operation of the system shown in FIG. 2, the ROM 24
Control programs and application programs are stored in the CPU 20, and when an address is supplied to the address bus 202 by access from the CPU 20, the program and the like are read from the corresponding address onto the data bus 201 and executed.

If you want to change some of the contents of the ROM 24, specify the setting address register 22 from the console 21 and input the address ("X" in the example shown) where the program (table) you want to change to the setting address register 22. Set to . Also, the contents of the new program (table) changed from the console 21 are stored in the ROM 2 in the RAM 25.
4 is stored at the same address X.

As a result, the CPU 20 sequentially accesses the ROM 24, and the comparison circuit 23 compares the address <X, > on the address bus 202 with the set address register 22.
When it is detected that the address (x) of ``-'' matches, the output 231 is generated. This output is directly supplied to the ROM 24 as an inhibition signal (inhibitor 1-: indicated by INH) input, inhibiting the operation in that cycle. Note that the INH signal may be a chip select signal (indicated by the mouth).

On the other hand, the coincidence output 231 from the comparator circuit 23 is inverted by the NOR circuit 26 and sent to the RAM 25 as an inhibition release signal (IN
(represented by H), and this RAM25 is input as
Drive to operate for access from 0.

At this time, the RΔM 25 is driven to read by inputting the address (X) from the address bus 202, reads out the changed data previously stored at that address, and outputs it to the data bus 201.

If the next address from the CPU 20 is not stored in the set address register, the address is supplied to the ROM 24, the corresponding data is read out, and the address is transferred to the data bus 2.
01.

In this way, patching is performed by replacing some data such as programs in the ROM 24 with the separately provided RAM 25.

By setting a plurality of addresses in the set address register 22 and writing new data to the same address in the RAM 25 for each set address, it is possible to perform rewriting at a plurality of addresses.

In addition, if the RAM 25 needs to retain its contents even when the power is turned off, the RAM 25 may be an EEPROM (Electrical
y Erasable and Programmable
The content can be reliably retained by using ``Read Only Memory'', and the same applies to the configurations of other embodiments described below.

In the case of this embodiment configuration, since the addresses of the ROM 24 and the RAM 25 are in a one-to-one correspondence, the RAM 2 has the same size as the address space that may be changed in the ROM 24.
You need to prepare 5.

Then, like when changing a table in ROM,
If the changed part is limited (same length as the original data), the change can be easily executed, but when changing the program, the amount of RAM that should be prepared cannot be limited (useless addresses This is disadvantageous because it creates space.

FIG. 3 shows a second embodiment of the configuration of the present invention.

In FIG. 3, 30 is a CPU, 31 is a console, 32 is a setting command register, 33 is a setting address register, 34 is a comparison circuit, 35 is a ROM, and 36 is a RAM.

To explain the operation of the configuration shown in Fig. 3, first, as a preparatory work, ① write the changed program from the console starting from the top address of RAM 36 (XX in the example shown), and finally the return address of ROM 35 (△△10). Write a JUMP command to m=where m is the changed high 1- or the number of words).

(2) Write a JUMP command to the beginning (XX) of 36 to R8 into the setting command register 32;

(2) Set the start address (hehe) of the program (table) to be changed in the ROM 35 in the setting address register 33 from the console 31;

To explain the operation after making such preparations, the CPU
30 outputs an address to the address bus 302 in order to avoid taking out the program from the ROM 35, and sequentially reads and executes the program.

The address on the address bus is compared with the setting address of the setting address register 33 in the comparison circuit 34, and both 7
When 1-res (△△) matches, the match output causes RO
Signal ○E (Outp
ut Enable).

This causes the data bus 30 to be transferred from the setting command register 32 to the
1, the above-mentioned JUMP instruction is output, and the CPU 30 reads and executes it.

Then, the CPU 30 sends the JUMP destination address (RA
Since the start address XX) of M36 is output to the address bus 302, the RAM 36 reads out the program (change program) at the start address and outputs it to the data bus 301.

After this, the CPU 30 sequentially specifies and accesses the addresses of the RAM 36, reads the JUMP instruction from the RAM 36, jumps to the address included in that instruction (10 meters to the return address △ to the ROM 35), and thereafter uses the ROM 36 Return to the address and proceed with the process.

In the case of configuration 2 of this embodiment, by assigning the address space to be different for the ROM 35 and the RAM 36,
While one is operating, the other will not.

Compared to the configuration shown in FIG. 2, the configuration 2 of the embodiment configuration shown in FIG. The feature is that the program length (high I number or number of words) before and after the change can be freely changed.

As a second modified configuration of the embodiment configuration shown in FIG. 3, there is the following configuration.

The amount of changes in instructions and tables is in units of one address (1 high, 1 -
11 words, etc.), but in this case, the third
The RAM 36 shown in the figure is made unused, and the changed instruction or the changed table data itself is written into the setting instruction register 32 (from the console). In this way, when the address to be changed is detected by the comparison circuit 34, the ROM 35 is inhibited and the setting instruction register 3
2 outputs the changed instruction or table data onto the data bus 301, and the CPU 30 receives and executes the instruction or data.

Next, a specific configuration example of the present invention shown in FIG. 4 will be described.

In Fig. 4, 40 is the CPU, 41 is the console, and 4 is the console.
2 is a setting address register, 43 is a comparison circuit, 44 is R
OM, 45 is a RAM, 401 is a control line, 402 is a data bus, and 403 is an address bus consisting of address lines AO to An.

Note that the most significant bit AO of the address bus is used to indicate memory selection, and indicates the ROM 44 at "'1°";
' Indicates RAM 45 when OP.

The configuration shown in FIG. 4 operates on the same principle as Embodiment 1 shown in FIG. An (AO is '1'')
When you enter each hint, one of the control lines 401 (■・0
WR) is driven and address data is set in the setting address register 42.

Also, in RAM4-5, AO from the console 41 “
At 0'', the other Al to An specify the same address as the address of the program before the change in the ROM 44, and write the contents of the new program.

When the CPU 40 outputs an address to the address bus 403 and reads out a program from the ROM 44, the address of the setting address register 42 and the address bus 4
Address 03 is manually input to the EOR circuit 431 for each hit to detect inconsistency for each hint. Then, when the outputs of all the EOR circuits are input to the NAND circuit 432, the output of the NAND circuit 432 will eventually generate a "0" output when both atlases match, and a "1" output when they do not match.

When the output is ANDed with AO of the address bus and NAND circuit 441, AO-"1" (ROM4
4 is selected) and both addresses do not match, a 0" output is generated, the σ West signal is not generated, and reading of ROM44 is permitted.AO="0" (RAM45 is selected) or both addresses match. At this time, a 1'' output (C3 signal) is generated and reading of ROM 4.4 is prohibited.

On the other hand, the output of the NAND circuit 432 is supplied to the AND circuit 451 and is input together with the AO of the address bus, and in the case of AO of the address bus - "'O" (RAM4.5 is selected), it is the output of AND4.51. The surface signal becomes 0' and the RAM 45 is driven. AO-“1” (ROM4
4) and the two addresses do not match, "'1 output is generated and the RAM 45 is not driven.AO-" 1
'' (ROM 44 is selected) and when both addresses match, an "o" output is generated and the RAM 45 is driven.

As a result, when both addresses match, the contents of the corresponding addresses A1 to An in the ROM 44 are not read out, and the RA
The contents of the same addresses A1 to An of M45 are read.

Three application examples that effectively utilize the features of the present invention are shown below.
~■ will be explained.

(2) When a bald program stored in the ROM of an information processing system is detected: Instead of creating a new ROM, the changes are stored in the RAM as soon as they are finalized, and the problem can be dealt with immediately without replacing the ROM. In this case, programs and tables can be changed depending on the installation location of the system and usage conditions (which differ for each user).

■When the bald ROM of the information processing system cannot be found, when the table is changed one after another, such as when the system is operated under various operating conditions (for example, changing the transfer speed of collected data), When investigating a different operating program by running it on a trial basis: In this case, conventionally it was necessary to create ROMs for all test cases, then stop the system and replace the ROMs. By applying this, even if a new investigation method is required at the installation site, it can be dealt with one after another on the spot.

■As a specific application example, when an information processing system that stores control programs and application programs in ROM is used as a collection station that collects data and transmits it to a higher-level station: In this case, conventionally, remote monitoring data As a transmission procedure, CDT (cyclic data
In this method, data from a large number of monitoring points is sequentially transmitted within a period of a fixed length, and the operation is repeated. For example, the data P1 to Pn of n monitoring points are PL, P2゜P3...
Transmit in order of Pn.

However, there is a transmission method in which the data sent within each period is not always from the same monitoring point. For example, if data Q1 to Qm from m monitoring points are sent once every m period, it is sufficient ( The data structure for one cycle at that time is as follows: rPl, P2...Pn, QIJ The subsequent cycles have the following structure.

rPl, P2 . . . Pn, Q2J From then on, data of monitoring points with different Q numbers are transmitted sequentially, and data transmission of Q is completed with one transmission. It is known to those skilled in the art that such a transmission method is referred to as a so-called 1-zabukomi, and hereinafter simply referred to as zabukomi.

While this subcomi transmission method is being executed by a ROM program, the data configuration of the subcomi must be urgently changed due to changes in the data to be monitored (for example, changes in the weather or the occurrence of an accident) or changes in usage conditions. The need arises. For example, there may be cases where it is desired to transmit the monitoring point data (Ql above) that was transmitted once in multiple cycles every cycle, or when it is desired to increase the number of monitoring points.

In such a case, the ROM patch method of the present invention can be used to
The operator (user) can immediately take action by changing the table in the ROM (a table that defines the configuration of the computer) using the RAM at the operation site, and it is also easy to return to the changed halo.

[Effects of the Invention] As described above, according to the present invention, in an information processing system in which a program is stored in a ROM, it is possible to change the program without stopping the system and without creating a new ROM. This can significantly reduce the work, cost, and time required for changes.

Furthermore, since there is no need to replace the ROM, programs can be changed without stopping the system, thereby eliminating the possibility of a drop in performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram showing a first embodiment of the configuration of the present invention, FIG. 3 is a diagram showing a second embodiment of the configuration of the present invention, and FIG. FIG. 1 is a diagram showing a specific configuration example of the present invention. In FIG. 1, 10 F ROM access source 11: Setting address detection means 1 2: ROM 1 3: RAM 14: Switching control means 101 Near address bus 102: Data bus

Claims (1)

[Claims] 1) In an information processing system in which a ROM (12) storing a program is connected to a ROM access source (10) by a bus (101, 102), an address at which the program in the ROM (12) is desired to be changed; a set address detection means (11) for detecting that the set address has been set and the set address has occurred on the bus (101); and a RAM (13) connected to the bus (101, 102) and storing the changed program. In response to the generation of the detection output of the setting address detection means (11), a prohibition signal is supplied to the ROM (12), and the RAM (13)
and a switching control means (14) for supplying a control signal to the
A ROM patch method in an information processing system characterized in that a modified program in a RAM (13) is executed while a ROM (12) access operation by a ROM access source (10) is continued. 2) In the description of claim 1, the control signal supplied from the switching control means (14) to the RAM (13) is a control signal for activating the RAM (13). ROM patch method for information processing systems. 3) In the description of claim 1, the switching control means (14) outputs a jump instruction to a specific address of the RAM (13), and at the end of the change program of the RAM (13). RO in an information processing system characterized by storing a jump instruction to a ROM (12)
M patch method. 4) A ROM patch method in an information processing system according to claim 1, wherein the control signal output from the switching control means (14) is preset changed data.