JPH0736536A - Programmable controller - Google Patents

Abstract

PURPOSE:To provide a programmable controller which can shorten the down time of an equipment and also can improve the securing efficiency for maintenance of the equipment. CONSTITUTION:A programmable controller is provided with a unit 1 of CPU which controls an external equipment serving as a controlled system, and a peripheral equipment 6 which is connected to the unit 1 and has a programming function. The unit 1 stores the access state given from the equipment 6 and secures it in a history storing area 14. Then the equipment 6 reads the access state out of the area 14 against the unit 1 and monitors the access state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention stores the access status of a CPU unit from a peripheral device as access history information inside the CPU unit to realize a reduction in downtime of the device and an efficiency improvement in maintenance work such as maintenance. Programmable controller.

[0002]

2. Description of the Related Art FIG. 13 is an explanatory diagram showing a schematic configuration of a conventional programmable controller system. In the figure, 1A is a CPU unit, which controls input / output signals to / from the external device 5 to be controlled,
It is connected to the peripheral device 6 via the RS422 cable 7. Reference numeral 2 is an input unit for inputting information from the external device 5 to the CPU unit 1A. Also,
An output unit 3 outputs information from the CPU unit 1A to the external device 5. Furthermore, 4 is a CPU
It is a base that supports the unit 1A, the input unit 2, and the output unit 3.

Further, 6 is a peripheral device, and the peripheral device 6
Is a wiring for creating a sequence program for executing the sequence processing of the CPU unit 1A, transferring the sequence program to the CPU unit 1A, and checking the connection between the Y contact of the programmable controller and the external device 5. It has a function of forcibly changing the state of the device such as the input information X, the output information Y, the data information D, etc. inside the CPU unit 1A in order to execute the check and debug the created sequence program. is doing.

FIG. 14 is a block diagram showing a hardware configuration of the CPU unit 1A, and in FIG.
Is a CPU (central processing unit) for executing the sequence program, 9 is a sequence program memory for storing the sequence program, 10 is an input port for reading a signal from the input unit 2, and 11 is an actual signal to the output unit 3. , 12 is a device memory area for storing input signal information from the input unit 2 and output signal information for the output unit 3, 1
Reference numeral 3 is a peripheral I / F (interface) unit that relays between the CPU unit 1A and the peripheral device 6, and 14A is a parameter area for storing parameters such as sequence program capacity and comment capacity.

FIG. 15 is an explanatory view showing a circuit monitor screen of a conventional programmable controller, in which the circuit is read in the peripheral device 6 while the sequence program of the programmable controller shown in FIG. It shows an example of execution. In the figure, 15 is a circuit readout screen, and 16 is a contact M.
10 (M is an internal relay device, 10 is a device number.
17 is a command [SET Y20] for setting Y20 when the contact M10 is turned on. Further, 18 indicates a circuit monitor screen, and 35 indicates an ON state of the device.

FIG. 16 is an explanatory diagram showing a connection configuration of the CPU unit 1A and the peripheral device 6, in which 22 is a keyboard of the peripheral device 6 and 23 is a sequence program in the CPU unit 1A and the sequence program is stored. PC for reading out the program capacity, which is the memory capacity to store, or parameters such as I / O allocation
A read key 24 is a PC write key for writing the sequence program created in the peripheral device 6 and the above parameters to the CPU unit 1A.

Next, the operation will be described. Figure 17
It is a flowchart which shows the process performed when the access request | requirement from the peripheral device 6 of the conventional programmable controller to the CPU unit 1A is carried out. This CPU
Data exchange between the unit 1A and the peripheral device 6 is executed via the peripheral I / F unit 13 shown in FIG. When the processing in FIG. 17 is executed, FIG. 15 and FIG.
In the sequence program set by Y20 when the contact M10 shown in FIG. 7 is turned on, first, it is determined whether or not there is a request from the peripheral device 6 side to forcibly turn on Y20 (S127), and the peripheral device 6 side outputs Y20. If it is determined that there is a request to forcibly turn ON, the request process for forcibly outputting Y20 is executed (S1).
28). After that, response data for forcibly outputting Y20 is set in the transmission buffer (S129), and this processing ends. As a result, the transmission buffer is transmitted to the peripheral device 6, and as a result, the peripheral device 6 turns on Y20 (35) even if the contact M10 is not turned on, and monitors the result.

Further, in the case of reading out the sequence program and parameters in the CPU unit 1A to the peripheral device 6 in the data exchange between the CPU unit 1A and the peripheral device different from the above, the peripheral shown in FIG. It can be read by the PC read key 23 of the device 6. Furthermore, when writing the sequence program or the parameter created by the peripheral device 6 to the CPU unit 1A, it can be written by the PC write key 24 of the peripheral device 6.

As described above, in the conventional programmable controller, the processing is executed for the access from the peripheral device 6 to the CPU unit 1A, but the access information is not protected.

Further, as a reference technical document related to the present invention, there is an "operation history storage device of information processing device" disclosed in Japanese Patent Laid-Open No. 56-99555. this is,
The present invention relates to an operation history storage device in which an operation of an instruction is known in an information processing device that performs information processing by reading an instruction in the storage device and decoding and executing the instruction.

Further, there is an "automatic operation system of a numerical controller" disclosed in Japanese Patent Laid-Open No. 3-230202.
This stores a series of operating procedures performed by the operator on the numerical control device in the operating history memory as operating procedure information,
The contents of the operation procedure information stored in the operation history memory are read out by an external instruction and reproduced.

Further, the "switch operation history collection method" disclosed in Japanese Patent Laid-Open No. 4-105140 relates to a switch operation history collection method connected to a data processing device in a computer system. Four
The "key simulator device" disclosed in Japanese Patent Publication No.-71016 is for saving a keyboard operation history of an operator station and reproducing and outputting the saved history on a display.

In addition, as reference technical documents related to the present invention, "electronic filing apparatus" disclosed in Japanese Patent Application Laid-Open No. 4-44133 and "Program debug support processing" disclosed in Japanese Patent Application Laid-Open No. 1-305446. System "," data processing system "disclosed in JP-A-2-126340," debug history storage system "disclosed in JP-A-63-75848, and JP-A-3-246736. "Control device", "Automatic operation system of numerical control device" disclosed in Japanese Patent Laid-Open No. 3-230202, and Japanese Patent Laid-Open No. 4-1051.
No. 40, "Switch operation history collection method", Japanese Patent Laid-Open No. 4-71016, "Key simulator device", Japanese Patent Laid-Open No. 3-202929, "Operation history". Analyzing device ", JP-A-3
"Design procedure support device" disclosed in JP-A-147023, "Operator console" disclosed in JP-A-3-25535, and "Numerical controller" disclosed in JP-A-3-163604. Japanese Patent Laid-Open No. 3-1
There is a "system automatic test method" disclosed in JP-A-02536 and a "bug finding method" disclosed in JP-A-2-297227.

[0014]

However, in the conventional programmable controller as described above, the processing is executed when the peripheral unit accesses the CPU unit. Was not maintained in the CPU unit or in peripheral devices. Therefore, when the entire programmable controller system goes down (fails) or when the sequence program processing changes, for example, the contents of access to the CPU unit from the peripheral device in the past cause the sequence program itself. When does not operate normally, the information is not recorded as a history, which makes it difficult to analyze the cause and spends a lot of time on maintenance such as repair of programs, resulting in poor work efficiency. there were.

In the "key simulator device" disclosed in the above-mentioned Japanese Patent Laid-Open No. 4-71016,
Although the keyboard operation history of the operator station is saved, even if the history of keyboard operation from the peripheral device to the CPU unit is left in the programmable controller system, the peripheral device and CP
It is difficult to analyze the access content itself regarding the actual exchange with the U unit. Therefore, if the contents of access to the CPU unit are not clear, the history cannot be effective for maintenance of programs later.

The present invention has been made in view of the above, and makes it possible to automatically analyze access information from a peripheral device to a CPU unit, and save the information to facilitate the peripheral device. It is an object of the present invention to provide a programmable controller that enables confirmation of the contents and realizes downtime of equipment and efficiency of maintenance work such as maintenance.

[0017]

In order to achieve the above-mentioned object, a programmable controller according to the present invention is provided.
In a programmable controller having a CPU unit for controlling an external device as a control target and a peripheral device connected to the CPU unit and having a programming function, the CPU unit stores an access state from the peripheral device and performs maintenance. The peripheral device reads the access state to the CPU unit from the history storage unit and monitors the access state.

Further, the capacity of the history storage means for storing the access state from the peripheral device in the CPU unit is arbitrarily set by the parameter setting in the peripheral device.

Further, the history information of the access state from the peripheral device to the CPU unit is read out from the history storage means and displayed on the screen.

A CPU unit for controlling an external device as a control target is connected to the CPU unit,
In a programmable controller having a peripheral device having a programming function, the CPU unit stores a history storage unit for storing and maintaining an access state from the peripheral device and history information stored in the history storage unit. History information clearing means for clearing, and the peripheral device reads the access state to the CPU unit from the history storing means and monitors it.
The history information is cleared by the history information clearing means.

[0021]

In the programmable controller according to the present invention, the CPU unit stores and preserves the information accessed from the peripheral device, and the peripheral device exchanges data with the CPU unit to read the access information and monitor the circuit. Sometimes the access status to the CPU unit is monitored.

In addition, the access status from the peripheral device is changed to CP.
The capacity of the area to be stored in the U unit is arbitrarily set by the parameter setting in the peripheral device, and the storage area is effectively used.

Further, the history information of the access state from the peripheral device to the CPU unit is read out from the CPU unit and displayed on the screen to improve the workability of confirming the history information.

Further, the history information clearing means provided in the CPU unit clears the history information of the access state to the CPU unit from the peripheral device stored in the CPU unit, and the storage capacity is effectively utilized.

[0025]

【Example】

[Embodiment 1] An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of a system of a programmable controller according to the present invention, showing a configuration of a programmable controller capable of maintaining access state history information from a peripheral device to a CPU unit. In the figure, reference numeral 1 denotes a CPU unit, which has a function of controlling an input / output signal with respect to an external device 5 to be controlled and a function of preserving information accessed from a peripheral device 6 via an RS422 cable 7. Reference numeral 2 is an input unit for inputting information to the CPU unit 1.

Reference numeral 3 is an output unit for outputting information from the CPU unit 1, and the information when the output is forcibly turned on / off on the monitor screen of the peripheral device 6 is also stored in the CPU unit 1. Stored in the access information storage area from the peripheral device in
It is configured so that it can be monitored. In addition,
Reference numeral 4 is a base that supports the CPU unit 1, the input unit 2, and the output unit 3.

Further, the peripheral device 6 creates a sequence program for executing the sequence processing of the CPU unit 1, and executes the sequence program.
To execute the wiring check and the debug of the created sequence program,
It has a function of forcibly changing device states such as input information X, output information Y, and data information D inside the CPU unit 1. 7A is an IC memory card,
7B is a floppy disk.

FIG. 2 is a block diagram showing a hardware configuration of the CPU unit 1, in which 8 is a CP of a microcomputer chip which executes a sequence program.
U, 9 are sequence program memories for storing sequence programs, 10 is an input port for reading a signal sent from the input unit 2, 11 is an output port for actually sending a signal to the output unit 3, and 12 is an input. A device memory area for storing input information from the unit 2 and output signal information for the output unit 3, 13 is C
Peripheral I / F that relays between the PU unit 1 and the peripheral device 6
Part, 14A is a parameter area existing on the same memory as the device memory 12, and 14 is also the device memory 1
2 is a history storage area for storing access history information for the CPU unit 1 from the peripheral device 6 existing on the same memory as 2.

FIG. 4 is an explanatory diagram showing a history storage area 14 for storing access information to the CPU unit 1 from the peripheral device 6 of the programmable controller. In the figure, the history storage area 14 stores access information composed of request data 14a and access date / time 14b. At the beginning of the history storage area 14, the access history number 14c from the peripheral device 6 to the CPU unit 1 is stored.

FIG. 5 is an explanatory view showing a circuit monitor screen in the peripheral device of the programmable controller, which shows a screen example in which the history of output Y from the peripheral device 6 being forcibly turned on is monitored, and 15 is a circuit. A read screen 18 is a circuit monitor screen.

Next, the operation will be described. Peripheral 6
When the CPU unit 1 is accessed from the above, the access process is conventionally executed only. On the other hand, in the present embodiment, as shown in FIG. The access information such as the ON / OFF state of the device and the bit device accessed to the area 14 or the current value of the word device is stored. This operation will be described based on the flowchart shown in FIG.

FIG. 3 is a flowchart showing a processing procedure in which the access information is stored in the history storage area 14 when the peripheral device 6 accesses the CPU unit 1. This operation is started when the sequence program is executed, and first, it is determined whether or not there is an access request from the peripheral device 6 to the CPU unit 1, for example, PC writing of the sequence program (S).
101). When it is determined in step S101 that there is no access request, this process is ended as it is. On the contrary, if it is determined in step S101 that there is an access request, the writing process of the sequence program to the programmable controller is executed (S102). After performing the processing for this access request, the response data is set in the transmission buffer (S103).

Next, the contents of the above access request are
It is determined whether it is a writing process or a reading process for the unit 1 (S104). In this step S104,
When it is determined that the writing process is performed, the request data is set in the history storage area 14 (S105). On the other hand, if it is determined in step S104 that the reading process is being performed, the response data is set in the history storage area 14 (S106). After the step S105 or step S106 is executed, the requested time (date and time) is set in the history storage area 14 (S107), and the series of processes of the exchange between the CPU unit 1 and the peripheral device 6 is completed.

On the circuit monitor screen shown in FIG. 5, M10 is normally displayed as the sequence program flow.
When (16) is turned on, Y20 (17) is set and turned on, but the operator uses the circuit monitor screen to turn Y20 (17) on, for example, 10:12 on August 4, 1992. When it is forcibly set to 27 minutes, and turned on, "Y20 black □ (ON state) 92/08/04
The status and date and time of the accessed device are monitored (10:12:27) (19). After that, Y20 (17) is again set to 1 on August 5, 1992.
If you forcibly reset and turn it off at the 5th order 27 minutes and 30 seconds, "Y20 □ (OFF state) 92/08/0
5 15:27:30 "new access information is monitored.

As described above, the access state from the peripheral device 6 to the CPU unit 1 is stored in the work area in the memory inside the CPU unit 1,
Since the peripheral device 6 has an area to be protected, and the peripheral device 6 has a function of reading and monitoring the access history from the access state storage area from the peripheral device 6 inside the CPU unit 1 when the circuit of the sequence program currently being RUN is monitored. In the event of a failure or a change in the sequence program processing, the history of access information to the CPU unit 1 in the past can be easily confirmed, and the maintenance work of the program can be easily performed. it can.

[Second Embodiment] Next, a second embodiment will be described. FIG. 6 shows a parameter area 1 provided in the CPU unit 1 of the programmable controller.
4A and 4A are explanatory diagrams showing an access history storage capacity area 21 from the peripheral device 6 to the CPU unit 1. FIG.

FIG. 7 shows the peripheral device 6 to the CPU unit 1
5 is a flowchart showing a process for securing an access history storage capacity area 21 necessary for storing access information for the history storage area 14;

In FIG. 7, the parameter capacity check of the CPU unit 1 is performed when the power of the CPU unit 1 is turned on and when the CPU unit 1 is stopped → run. First, the capacity of each function is checked (S110). That is, here, the comment capacity for setting whether or not to add a comment to the sequence program, and how much of the expansion memory area capacity that can be used by setting the capacity with parameters are set. To confirm. Further, a capacity check is performed to see if the set capacity of the sequence program is within the range of the CPU unit 1 used (S111). In addition,
In this case, if it is out of the range, it is processed as an error.

After the step S111 is executed, the peripheral device 6 has the function of setting the access history storage capacity for the CPU unit 1 in the parameter setting in the peripheral device 6, so that the history storage area capacity is set here. It is determined whether or not there is (S112). In step S112, if it is determined that the history storage area capacity is set, the parameter area 14
An area for the history storage area setting capacity is secured in A (S113), and this processing ends.

In this way, the operator sets the access history storage capacity for the CPU unit 1 from the peripheral device 6, so that the parameter is transferred to the access history storage capacity area 21 for the CPU unit 1 from the peripheral device 6 in the parameter area 14A. CP from the peripheral device 6 as shown in FIG. 2 based on the capacity.
The history storage area 14 for the U unit 1 is secured.

As described above, the parameter area 14A of the CPU unit 1 includes the storage history capacity area of the access state from the peripheral device 6 to the CPU unit 1, so that the access state from the peripheral device 6 is stored in the CPU unit 1. The parameter for storing is not fixed and can be freely set by the operator, and the memory can be used effectively without waste.

[Third Embodiment] Next, a third embodiment will be described. FIG. 8 is an explanatory diagram showing a schematic configuration of the CPU unit 1 in the programmable controller and a peripheral device that creates a sequence program and exchanges with the CPU unit 1. In the figure, reference numeral 22 denotes a keyboard of the peripheral device 6, in which several kinds of input keys are arranged. In particular, 23 is a PC read key for reading the sequence program and parameters in the CPU unit 1, 24 is a PC write key for writing the sequence program and parameters created by the peripheral device 6 in the CPU unit 1, and 25 is the CPU unit 1. Access history read key 2 for reading the access history for the CPU unit 1 from the peripheral device 6 stored therein, 2
Reference numeral 6 denotes an access history screen display key for displaying an access history of the CPU unit 1 from the peripheral device 6 read by the access history read key 25.

FIG. 9 is an explanatory view showing an access history display screen from the peripheral device 6 to the CPU unit 1 in the peripheral device 6 in the programmable controller. In the figure, 27 is an access history display screen, 28 and 31 are dates when the peripheral device 6 accesses the CPU unit 1, 29 and 32 are CPs from the peripheral device 6.
Time of access to U unit 1, 30 and 3
Reference numeral 3 indicates the contents accessed from the peripheral device 6 to the CPU unit 1, respectively.

Next, the operation will be described. In FIG. 8, when the sequence program, parameters, etc. in the CPU unit 1 are read from the peripheral device 6 by the PC read key 23, or the sequence program, parameters, etc. created in the peripheral device 6 by the PC write key 24 are read by the CPU unit. When the data is written in 1, the date and time when the CPU unit 1 is accessed, as in the case of forcibly changing the ON / OFF state of the bit device and the current value of the word device described in the first embodiment. , And the processing content is the CPU unit 1
Is stored in the storage area in.

FIG. 10 is a flowchart showing a processing procedure for displaying the access history from the peripheral device 6 to the CPU unit 1. In FIG. 10, after the sequence program is executed, the screen display process of the access history from the peripheral device 6 to the CPU unit 1 is started. First, the access date and time from the peripheral device 6 to the CPU unit 1 is read from the history storage area 14 ( (S116), the access date and time is displayed on the screen (S117). Then, the access status from the peripheral device 6 to the CPU unit 1 is read from the history storage area 14 (S118), and the access status is displayed on the screen (S119). After that, it is determined whether or not the display for the number of access histories is completed by the above series of processing (S120), and when it is determined that the display for the number of access histories is not completed, the process returns to step S116. Then, the same processing is repeatedly executed.
If it is determined in step S120 that the display for the number of access histories has been completed, this processing ends.

The CPU unit 1 from the peripheral device 6
When confirming the access history for the CPU unit 1, the access history read key 25 shown in FIG.
The access history for the peripheral device 6 from is read. After that, when the access history screen display key 26 is selected, the screen as shown in FIG. 9 is displayed and output.

FIG. 9 is an example of an access history from the peripheral device 6. Operator, August 4, 1992, 1
When the internal relay device M0 is forcibly reset on the circuit monitor screen of the peripheral device 6 at 0:00:11, it is displayed on the screens indicated by reference numerals 31, 32 and 33 in the figure. . In addition, the operator
C: Peripheral device 6 at 21:27:30 on August 4, 2012
When the PC writing process for the PU unit 1 is executed, it is displayed on the screens indicated by reference numerals 28, 29 and 30 in the figure.

Since the storage capacity of the access history from the peripheral device 6 is limited in the CPU unit 1, the access history information for each sequence program can be stored in the floppy disk 7B or the IC memory card 7A ( (See FIG. 1).

As described above, the peripheral device 6 has a CPU.
Access history read key 25 for reading information in the access history area from the peripheral device 6 inside the unit 1
Since the access history screen display key 26 for displaying the history information of the access state from the peripheral device 6 to the CPU unit 1 is provided on the screen, the operator confirms the access state to the CPU unit 1 and the history by the peripheral device 6. be able to. The access status to the CPU unit 1 and its history are recorded together with the sequence program in the floppy disk 7B or I disk.
Since it can be stored in the C memory card 7A, the sequence program and the access history can be reconfirmed at the same time.

[Embodiment 4] Next, a fourth embodiment will be described. FIG. 11 shows a CPU unit 1 according to this embodiment.
FIG. 3 is a block diagram showing the hardware configuration of the above. This configuration is different from the hardware configuration shown in FIG. 2 in that a history clear dedicated device 34 that executes a process of clearing the history of access states from the peripheral device 6 to the CPU unit 1 is performed.
Is provided in the CPU unit 1, and the other parts have the same configuration as that shown in FIG.

Next, the operation will be described. Figure 12
6 is a flowchart showing an access state history clearing process from the peripheral device 6 to the CPU unit 1. In the figure, when there is a request for history clearing processing, this processing is started, and first, it is determined whether or not there is a history clearing request due to the history clearing dedicated device 34 being turned on (S123). If it is determined in step S123 that the history clear request has been issued, the contents stored in the history storage area 14 are cleared (S12
4) Then, this process ends. In addition, the above step S123
When it is judged that there is no history clear request,
This processing is ended as it is.

According to the above embodiments, the CPU unit 1
The device memory of the peripheral device 6 is provided with the history clear dedicated device 34 for clearing the history information of the access state from the peripheral device 6 to the CPU unit 1. By turning on the history clear dedicated device 34, the CPU from the peripheral device 6 is
It is possible to clear the access state history information for the unit 1, save unnecessary access information, and effectively utilize the limited access information storage area in the CPU unit 1.

[0053]

As described above, according to the programmable controller of the present invention, the work area in the memory inside the CPU unit is provided with an area for storing and maintaining the access state from the peripheral device to the CPU unit. The peripheral device reads the access history from the access status storage area from the peripheral device inside the CPU unit and monitors it when monitoring the circuit of the sequence program currently being RUN. When occurs,
The history of access information to the CPU unit in the past can be easily confirmed, and further, the maintenance work of the program can be easily carried out.

Further, since the storage area capacity area for storing the access status from the peripheral device to the CPU unit is provided in the parameter area of the CPU unit, the parameter for storing the access status from the peripheral device in the CPU unit is not fixed. Can be set freely by the operator, and the memory can be used effectively without waste.

Further, the peripheral device is provided with an access history read key for reading the information in the access history area from the peripheral device inside the CPU unit, and the history information of the access state to the CPU unit from the peripheral device is displayed on the screen. Since the access history screen display key is provided, the operator can confirm the access status to the CPU unit and its history by the peripheral device.
Further, since the access state to the CPU unit and its history can be saved together with the sequence program in the floppy disk or IC memory card, the sequence program and the access history can be reconfirmed at the same time.

Further, the device memory of the CPU unit is provided with a history clear dedicated device for clearing history information of access status from the peripheral device to the CPU unit, and by turning on the history clear dedicated device, the CPU from the peripheral device is turned on. It is possible to clear the access state history information for the unit, save unnecessary access information, and effectively use the limited access information storage area in the CPU unit.

As a result, the access information to the CPU unit from the peripheral device can be automatically analyzed, and
By storing the information, the contents can be easily confirmed in the peripheral device, and downtime of the device can be shortened and maintenance work such as maintenance can be efficiently performed.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a schematic configuration of a system of a programmable controller according to the present invention.

FIG. 2 is a block diagram showing a hardware configuration of a CPU unit shown in FIG.

FIG. 3 is a flowchart showing a processing procedure in which access information is stored in a history storage area when an access is made to a CPU unit from a peripheral device.

FIG. 4 is an explanatory diagram showing a history storage area for storing access information to the CPU unit from the peripheral device of the programmable controller according to the present invention.

FIG. 5 is an explanatory diagram showing a circuit monitor screen in a peripheral device of the programmable controller according to the present invention.

FIG. 6 is an explanatory diagram showing a parameter area provided in the CPU unit and an access history storage capacity area from the peripheral device to the CPU unit in the programmable controller according to the present invention.

FIG. 7 is a flowchart showing a process for securing an access history storage capacity area required for storing access information for a CPU unit from a peripheral device in the history storage area.

FIG. 8 is an explanatory diagram showing a configuration of a CPU unit in a programmable controller according to the present invention and peripheral devices that create a sequence program and exchange with the CPU unit.

FIG. 9 is an explanatory diagram showing an access history display screen from the peripheral device to the CPU unit in the peripheral device of the programmable controller according to the present invention.

FIG. 10 is a flowchart showing a procedure for displaying a history of access from a peripheral device to a CPU unit.

FIG. 11 is a block diagram showing a hardware configuration of a CPU unit according to the present invention.

FIG. 12 is a flowchart showing an access state history clearing process for a CPU unit from a peripheral device according to the present invention.

FIG. 13 is an explanatory diagram showing a schematic configuration of a conventional programmable controller system.

14 is a block diagram showing a hardware configuration of a CPU unit shown in FIG.

FIG. 15 is an explanatory diagram showing a circuit monitor screen of a conventional programmable controller.

FIG. 16 is an explanatory diagram showing a connection configuration and the like between a conventional CPU unit and peripheral devices.

FIG. 17 is a flowchart showing a process executed when an access request to a CPU unit is made from a peripheral device of a conventional programmable controller.

[Explanation of symbols]

 1 CPU Unit 2 Input Unit 3 Output Unit 4 Base 5 External Device 6 Peripheral Device 7A IC Memory Card 7B Floppy Disk 8 CPU 9 Sequence Program Memory 12 Device Memory Area 14 History Storage Area 14A Parameter Area 25 Access History Read Key 26 Access History Screen Display key 34 History clear device

Claims (4)

[Claims] 1. A C for controlling an external device as a control target.
In a programmable controller having a PU unit and a peripheral device connected to the CPU unit and having a programming function, the CPU unit includes history storage means for storing and maintaining an access state from the peripheral device, The programmable controller, wherein the peripheral device reads an access state to the CPU unit from the history storage means and monitors it. 2. The capacity of the history storage means for storing the access state from the peripheral device in the CPU unit is arbitrarily set by parameter setting in the peripheral device. Programmable controller. 3. The history information of the access status from the peripheral device to the CPU unit is read from the history storage means and displayed on the screen.
Programmable controller described. 4. A C for controlling an external device as a control target.
In a programmable controller having a PU unit and a peripheral device that is connected to the CPU unit and has a programming function, the CPU unit includes a history storage unit for storing and maintaining an access state from the peripheral device; History information clear means for clearing history information stored in the history storage means, and the peripheral device reads the access state to the CPU unit from the history storage means, monitors it, and clears it by the history information clear means. A programmable controller characterized by: