JPS58111938U - Ceramic packages for semiconductor devices - Google Patents

Ceramic packages for semiconductor devices

Info

Publication number
JPS58111938U
JPS58111938U JP1982009576U JP957682U JPS58111938U JP S58111938 U JPS58111938 U JP S58111938U JP 1982009576 U JP1982009576 U JP 1982009576U JP 957682 U JP957682 U JP 957682U JP S58111938 U JPS58111938 U JP S58111938U
Authority
JP
Japan
Prior art keywords
semiconductor devices
ceramic packages
melting point
low melting
ceramic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982009576U
Other languages
Japanese (ja)
Inventor
櫻井　正彦
Original Assignee
株式会社東芝
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社東芝 filed Critical 株式会社東芝
Priority to JP1982009576U priority Critical patent/JPS58111938U/en
Publication of JPS58111938U publication Critical patent/JPS58111938U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図ａ、　　ｂはそれぞれ従来の半導体装置用セラミ
ック・パッケージの斜視図および断面構成図、第２図は
上記第１図ａ、　　ｂの半導体装置用セラミック・パッ
ケージにおける素子の固着方法を説明−するための図、
第３図はこの考案の一実施例番と係る半導体装置用セラ
ミック・パッケージの断面構成図である。 １１ａ、　　１１ｂ−−−セラミック、１２ａ、　　１
２ｂ−・・素子固着用低融点ガラス層、１３ａ、１３ｂ
・・・封止用低融点ガラス層、１４・・・リードピン、
１５・・・素子（チップ）、１８・・・凹部。Figures 1a and 1b are respectively a perspective view and a sectional view of a conventional ceramic package for semiconductor devices, and Figure 2 illustrates a method for fixing elements in the ceramic package for semiconductor devices shown in Figures 1a and 1b. diagram for,
FIG. 3 is a sectional view of a ceramic package for a semiconductor device according to an embodiment of the invention. 11a, 11b---Ceramic, 12a, 1
2b--Low melting point glass layer for element fixation, 13a, 13b
... Low melting point glass layer for sealing, 14 ... Lead pin,
15... Element (chip), 18... Recessed portion.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体素子の載置部に低融点ガラスを塗布し、素子を固
着するセラミック製の半導体装置用パッケージにおいて
、低融点ガラス層の素子載置部に素子形状に対応した凹
部を形成したことを特徴とする半導体装置用セラミック
・パッケージ。A ceramic package for a semiconductor device in which a low melting point glass is applied to a mounting part of a semiconductor element to fix the element, characterized in that a recess corresponding to the shape of the element is formed in the element mounting part of a low melting point glass layer. Ceramic packages for semiconductor devices.
JP1982009576U 1982-01-27 1982-01-27 Ceramic packages for semiconductor devices Pending JPS58111938U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982009576U JPS58111938U (en) 1982-01-27 1982-01-27 Ceramic packages for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982009576U JPS58111938U (en) 1982-01-27 1982-01-27 Ceramic packages for semiconductor devices

Publications (1)

Publication Number Publication Date
JPS58111938U true JPS58111938U (en) 1983-07-30

Family

ID=30022202

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982009576U Pending JPS58111938U (en) 1982-01-27 1982-01-27 Ceramic packages for semiconductor devices

Country Status (1)

Country Link
JP (1) JPS58111938U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221362A (en) * 1994-01-28 1995-08-18 Matsushita Electron Corp Magnetic sensor device, its manufacture, and manufacture of magnetic material used therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07221362A (en) * 1994-01-28 1995-08-18 Matsushita Electron Corp Magnetic sensor device, its manufacture, and manufacture of magnetic material used therefor

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