JPS58111587A - Automatic gain controlling circuit - Google Patents

Abstract

PURPOSE:To attain excellent AGC performance independently of waveform distortion of a video signal, by controlling a discharge circuit with a peak detection output of a synchronizing signal and outputting a key pulse for automatic gain control based on the output of a discharge circuit. CONSTITUTION:A synchronizing signal is obtained via a variable gain circuit 5 and a synchronizing signal separation circuit 6 and applied to a peak detection circuit 1. The circuit 1 and a minute constant current discharge circuit 2 sample a peak potential of the synchronizing signal and a discharge drop is produced at the non-sampling period. The output is compared with a reference potential at comparators 11 and 13, logical product is taken at an AND circuit 14 to obtain a pulse not including the front edge of the back porch of the video signal. The pulse is applied to a detected signal generating circuit 8 as the key pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for controlling video signal
This invention relates to an integrated circuit suitable for a 1gi circuit (hereinafter abbreviated as F, t; C).

A for recording video signals usually used in VTRs, etc.
In the GC circuit, a video signal with a white pulse added to the back porch of the synchronization signal is generated as the test wave signal.
, AGC system No. 1 g is set so that the amplitude from the sync tip to the white level of the bidet No. 1g is constant.

Conventionally, as shown in FIG. 1, an integrated circuit for adding the white pulse to a video signal in a refined manner is composed of a peak transverse wave circuit 1, an IEflL discharge circuit 2 and a comparator 3. , equivalently the trailing edge of the input synchronization signal i4 is the extended pulse. Conan for peak Ilt wave? 4, the power of monolithic IC is IQpFg, and the discharge current at that time is 10, an
2 degrees, but it can be obtained relatively easily with a resistance bias method current sink circuit, and integration has been realized. The Ki# side will be further explained using the operation explanatory diagram of FIG. Figure 2 (α)
From the video signal that is the output of the variable gain circuit 5 shown in
P4 period jIliIm path 6 obtained through the crisis Figure 2 (j
) is supplied to the peak detection circuit 1,
The peak of the sync signal is sampled. The sampled potential drops across the non-temple M in the minute constant current discharge circuit 2, and the output of the discharge circuit 2 becomes as shown in FIG. 82(c). The signal in Figure 2C) is the comparison potential (A) given by the reference voltage source 7 [shown by the broken line in Figure 2C].
If the signal shown in Figure 2 (C) is higher than the comparison potential (A), a high potential is given, and if it is lower than the comparison potential (A), a low potential is supplied from the comparator 3. A pulse as indicated by K is generated and inputted to the test wave signal generation circuit 8 as a key pulse.

In the test wave signal generation circuit 8, only during the above key pulse period,
A self-pulse is generated by calculating the potential difference between the video signal inputted from the other side and the syn-edge lag, and the video signal is added to the signal to obtain a transverse wave signal as shown in Figure 7s2 (#), and the detection circuit 9 is Through this, he controlled approximately 5 of the town's Henri stations.

However, in the above-mentioned conventional technology, due to the influence of the characteristic of Takeshi Hadami in the front stage of the AGC circuit #F, the leading edge of the bank pouch as shown in FIG. When input, if the pedestal level during the key pulse period has the above-mentioned rise, the added white pulse becomes as shown in Fig. 3 (6) K. Therefore, the test wave signal becomes as shown in Fig. 5 (-). The waveform becomes as shown in , the output of the detection circuit 9 increases by the amount of increase, the gain of the variable gain circuit decreases, and the amplitude of the video signal becomes smaller than the level of FTrjiI.

The purpose of this WA@ is to eliminate the drawbacks of the prior art and to
An object of the present invention is to provide an #& product circuit for AGC which has good AGC performance regardless of waveform distortion at the leading edge of a bank pouch of a video signal inputted to a GC circuit.

In order to achieve the above object, the present invention provides a key pulse J
As an integrated circuit, a slope pulse t with a slope is generated at the trailing edge of the synchronization signal using an integrated peak detection path and a minute constant current discharge circuit, and a comparison potential across the slope pulse is generated. Moreover, only when the potential of the gradient pulse is at the threshold of the comparison potential 211, a high potential pulse t is generated and used as a key pulse. That is, the first comparison potential removes the back porch Ii1 part of the synchronous Ig from the key pulse period, and the second comparison potential determines the end of the key pulse, thereby eliminating the influence of waveform distortion occurring in the front part. It is something to do.

The present invention will be explained below using an example. FIG. 4 is a diagram showing an embodiment of the AGC collection lateral d path of the present invention, and the fifth figure is a diagram illustrating the present invention in detail. 4th #! In J, parts that are equivalent or identical to those of the conventional example up to the point shown in FIG. 1 are given the same numbers. Now, in the conventional example, a video signal as shown in FIG. 5 (α) that deteriorates the A'GC characteristic is
When inputted to the circuit, a synchronizing signal as shown in FIG. Supplied. The peak detection circuit 1 and the minute constant LIC current discharge circuit Ms2 sample the peak threshold value of the synchronizing signal, and during the non-sampling period, the signal IIc drops, resulting in a signal as shown in FIG. 5 (CC).

The signal in Fig. 5 (C) is given by the reference voltage source 1o and is shown as the first comparison (C1) (Fig. 5 CC) by the t/C broken line]
and a reference voltage source 12.

Comparison potential (c) [shown in Figure 5(d) with a single point @-]
The output of the comparator 11 is Cd) in FIG. 5, and the output of the ratio 42 and the output signal 15 is as shown in FIG.

Next, when the AND circuit 14 performs an AND operation on the outputs of the softeners 11 and 13, a pulse is obtained that does not include the leading edge of the back porch of the video signal, as shown in Figure 5).
Test wave signal generation circuit as key pulse! 3. Therefore, the gate configuration signal is shown in Figure 5 (!i).
As shown in the figure, a white pulse with no busy or back-up is added, and the deterioration of the AGC characteristic can be eliminated. In addition, as the peak detection capacitor 4, as explained earlier in the conventional example, a single direct current (10 pF
- degree), a signal such as jg5s(C)K can be sufficiently obtained, and the entire structure of the present invention can be easily integrated.

FIG. 6 shows a specific example of an integrated circuit according to the present invention.

In Figure N6, parts that are equivalent or identical to those in Figures N1 and 4 are given the same honor symbol. The peak transverse wave flat is generated by transistor 15 and capacitor t4, and transistor 16.
The 17% resistors 18, 19, and 20 constitute a small constant current discharge circuit 2 using a resistance bias method current sink circuit. The transistor 21 and the resistor 22 receive the signal from the peak detection circuit 1 and the minute constant current discharge (Igl path 2) at high impedance, and the transistors 25 and 24 and the constant current source 25
Comparison a15 consisting of % resistance 26° reference voltage l112, transistors 27, 28, constant current source 29, resistor 50
, is supplied to a comparator 11 consisting of a reference voltage source 10.

The resistor 51 obtains an AND signal of the outputs from both the comparators 11 and 15, and supplies it to a high-input, low-output impedance circuit consisting of a transistor 32 and a resistor 55. Then, a key pulse that does not include the front edge of the back porch is output from the emitter of the transistor 23 to the test wave signal generation circuit 8 in the next stage.
This means that integration can be achieved with a relatively simple circuit.

As described above, according to the present invention, it is possible to realize an AGC integrated circuit that has good AGC performance regardless of the waveform distortion of the video signal input to the AGC 1 path and is suitable for integration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional AG/CMQ product circuit. Figure 82 and #I3 are explanatory diagrams of the conventional example, Figure 4 is a diagram illustrating an embodiment of the present invention, Figure N5 is a diagram illustrating details of the present invention, and Figure 6 is a specific circuit of the present invention. It is a figure which shows an example. In the diagram, 1...Peak detection circuit 2...Imitation small constant current power circuit! , 11, 13 - Comparator 6 - Synchronization separation circuit 8 - Test wave signal generation circuit 14 - ANI) circuit. i3 figure! +rfU Figure 5】-〇 Fish mouth

Claims (1)

[Claims] 1. A peak detection circuit into which the split layer synchronization No. 1 is input, a discharge circuit connected to the output of the peak detection circuit, and a first and second circuit to which the output of the discharge circuit is supplied. comprising at least a comparator and a maw path to which the outputs of both comparators are supplied;
A circuit for self-excitation gain control, characterized in that the output of the oscilloscope is used as a key pulse for an N1M gain IA control circuit. 2. Both of the above comparators are each configured with a differential excitation amplifier a consisting of a pair of transistors, and one pair is connected to the above output 1 IC1 [2 When the quasi-voltage voltage of the comparators 2 and 4 is low, the collector current of each of the transistors in the pair is interrupted by using a common resistor connected to the collector of the transistor,
I of the patent m characterized by configuring the above-mentioned ring circuit
[Circuit for self-excitation gain control of Orihoki 1st term.