JPS5811074Y2 - Variable frequency oscillation circuit using PUT - Google Patents

Description

[Detailed Description of the Invention] This invention relates to an improvement of a variable frequency oscillation circuit using a PUT.

A circuit shown in FIG. 1 has been used as a conventional circuit of this type.

In the figure, 1 is a DC power supply, 2 is a charging capacitor that is charged at a constant time constant by the DC power supply 1, 3 is a charging resistor that charges this charging capacitor 2, and 4 and 5 are connected to both ends of the DC power supply 1. The gate bias resistor 6 is connected to a PUT whose cathode is connected to the negative pole of the DC power supply 1, and 7 is a capacitor discharge current resistor connected between the connection point of the charging capacitor 2 and the charging resistor 3 and the anode of the PUT 6. Limiting resistance, 8
A diode 9 is connected between the connection point of the resistors 4 and 5 and the gate of the PUT 6 to prevent current from flowing into the gate of the PUT 5 from a variable DC power supply (to be described later) when the PUT 6 is turned on and destroying the PUT 6. is the above PUT6
A variable DC power supply 10 changes the gate bias of the circuit to change the oscillation frequency of the circuit, 10 is a resistor 4 whose voltage of the variable DC power supply 9 is changed.
, 5, the circuit oscillates at a frequency determined by the divided potential of the resistors 4 and 5, and conversely, when the voltage of the variable DC power supply 9 is higher than the divided potential of the resistors 4 and 5, the voltage of the variable DC power supply 9 is lower than the divided potential of the resistors 4 and 5. This is a transistor that allows the circuit to operate at a frequency determined by 9.

Next, the operation will be explained.

When the voltage divided by the resistors 4 and 5 is higher than the voltage of the variable DC power supply 9, the voltage of the charging capacitor 2 becomes higher than the former, and vice versa, when the voltage of the charging capacitor 2 becomes higher than the voltage of the variable DC power supply 9, the voltage of the charging capacitor 2→limiting resistor 7→PUT 6 increases. A gate current flows from the anode to the gate of PUT6 to diode 8, turning on PUT6.

When PUT6 is turned on, the charge in the charging capacitor 2 is discharged through the limiting resistor 7 and PUT5.

Until the discharge of this charging capacitor 2 is completed, P
UT6 remains on.

At that time, from the DC power supply 9 through the transistor 10, the PU
Diode 8 prevents current from flowing into the gate of T 6 and destroying PUT 6.

When the charging capacitor 2 has finished discharging, the PUT 6 is turned off and the above process is repeated again.

FIG. 2 is an operating waveform diagram of each part of the circuit of FIG. 1, and FIG. 3 is a characteristic diagram showing the voltage dependence of the oscillation frequency.

As is clear from FIG. 2, in the conventional circuit, no reverse bias is applied between the anode and gate of PUT 6 when PUT 6 is off due to diode 8 (see FIG. 2C).

Furthermore, the commercially available PUT6 has an ultra-high sensitivity and is characterized by being able to be triggered with a minute gate current.

Therefore, if used without gate reverse bias and without resistance between the anode and gate as shown in Figure 1, the PUT
This causes a drop in breakdown voltage and is much more prone to noise malfunctions than general thyristors.

Also, as mentioned above, if a resistor is connected between the anode and the gate, P
The gate trigger current of the UT6 increases significantly (10 to 100 times), making it impossible to take advantage of the high sensitivity of the PUT6, and the circuit no longer operates satisfactorily.

Therefore, even if the conventional circuit shown in FIG. 1 can be used in terms of voltage resistance, it cannot be used in locations where induced noise or the like occurs.

In this invention, in order to eliminate the drawbacks of the conventional circuit, the diode 8 of the conventional circuit is inserted between the gate bias resistors 4 and 5, so that a reverse bias is applied between the anode and the gate of the PUT 6 when the PUT 6 is off. The purpose is to significantly improve the noise margin of PUT6.

An embodiment of this invention will be described below with reference to the drawings.

In Figure 4, 1 is a DC power supply, 2 is a charging capacitor that is charged by the DC power supply 1 at a constant time constant, 3 is a charging resistor that charges this charging capacitor 2, and 4 and 5 are the DC power supply 1. A gate bias resistor 8 connected to both ends is connected between the resistors 4 and 5, and when PUT5 is turned on, P
Current flows into the gate of UT6 from DC power supply 9 and the PU
A diode to prevent T6 from being destroyed; 6 is a PUT whose cathode is connected to the negative pole of the DC power supply 1; 7 is a capacitor discharge connected between the connection point of the charging capacitor 2 and charging resistor 3 and the anode of the PUT 6 Current limiting resistance, 9 is the above P
A variable DC power supply 10 changes the gate bias of the UT 6 and changes the oscillation frequency of the circuit, and when the voltage of the variable DC power supply 9 is lower than the potential divided by the resistors 4, 5 and the diode 8, the voltage of the resistors 4, 5 and the diode 8 is changed. The circuit oscillates at a frequency determined by the divided potential, and conversely, when the voltage of the variable DC power supply voltage 9 is higher than the divided potential by the resistors 4, 5 and the diode 8, the circuit operates at the frequency determined by the variable DC/current power supply. It is a transistor that

Next, the operation of this circuit will be explained with reference to FIG. 5, which is an operation waveform diagram of each part.

When the voltage divided by the resistors 4 and 5 and the diode 8 is higher than the voltage of the variable DC power supply 9, the charging voltage of the charging capacitor 2 becomes higher than the former, and vice versa, when the charging voltage of the charging capacitor 2 becomes higher than the latter. →Anode of PUT6→PUT
A gate current flows from the gate of PUT 6 to the diode 8 and then to the resistor 5, and PUT 6 is turned on.

When PUT6 turns on, the charge in charging capacitor 2 is discharged through limiting resistor 7 and PUT6.

Until the discharge of this charging capacitor 2 is completed, the PU
T6 remains on.

At this time, the diode 8 prevents current from flowing from the variable DC power supply 9 to the gate of the PUT 6 through the transistor 10, thereby preventing destruction of the PUT 6.

When the charging capacitor 2 is completely discharged, the PUT 6 is turned off and the above process is repeated again.

In the case of this circuit, as shown in the voltage waveform diagram between the anode and gate of PUT 6 in FIG. 5C, the PU
A reverse bias is now applied between the anode and gate of T6.

In this way, according to the circuit shown in FIG. 4, when PUT is off, P
Since a reverse bias is applied between the UT anode and gate,
PUT breakdown voltage does not deteriorate and malfunctions due to noise are greatly improved, and noise malfunctions are no longer a problem in practice.

Of course, even though a reverse bias was applied to the gate of the PUT to improve malfunction, when the PUT was turned on, current did not flow from the variable DC power supply and destroy the PUT, and the circuit operated as before. do.

Incidentally, even if the transistor 10 in FIG. 4 is replaced with a diode 11 as shown in FIG. 6, the same effect can be obtained.

This invention can also be widely applied to thyristor trigger circuits, timer circuits, etc.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional variable frequency oscillation circuit, Figure 2 is a diagram of the operating waveforms of each part, Figure 3 is a diagram showing the voltage dependence of the oscillation frequency, and Figure 4 is an example of an embodiment of this invention. FIG. 5 is an operational waveform diagram of each part thereof, and FIG. 6 is a circuit diagram showing another embodiment of this invention. In the figure, 1 is a DC power supply, 2 is a charging capacitor, and 3
is a charging resistor, 4 and 5 are gate bias resistors, and 6 is P
UT, 7 is a limiting resistor, 8 is a diode, 9 is a variable DC power supply, and 10 is a transistor. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A charging capacitor that is charged at a constant time constant by a first power supply, two gate bias resistors for setting gate potential connected to the first power supply, and a first gate bias resistor connected between these two gate bias resistors. a transistor having an emitter connected to the cathode of the first diode, a collector connected to the first power source, and a base connected to the second variable power source, a gate connected to the anode of the first diode, and a transistor connected to the charging capacitor. A variable frequency oscillation circuit composed of an n-gate thyristor whose cathode is connected to the negative pole of the power source of the anode foil 1.