JPS5810915B2 - Time division multiplexing still image transmission device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a still image transmission device using a time division multiplex communication method.

In a still image transmission system using a time division multiplex communication method that transmits image data to one or more receivers using a single communication line, the transmitter side transmits image signals to one
Store a field or one frame, convert it to still image data, and before sending the image data, send the address code representing the selected line (the other party to which the image data is sent), and then send the image data. do.

On the receiving side, the address code is detected in front of a plurality of receiving units, and the line selected on the transmitting side is selectively switched and the image data is sent to the receiving unit.

The receiving section reproduces the image data into a still image signal.

When performing multiplex communication using this method, if the address detection circuit on the receiving side incorrectly detects the address code and connects to a line that was not selected on the sending side, the image data will be sent to the connected receiving section. The still image signal will be played back.

In other words, still images that are irrelevant to other recipients are sent.

In a video conferencing system, which is the main application of the still image transmission device, and in which it is desired to maintain relative secrecy, there is a disadvantage in that the occurrence of such an erroneous connection causes a significant disadvantage to the users of this system.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a time-division multiplex communication still image transmission device that prevents transmitted image data from being reproduced by a wrongly connected receiver even if a wrong connection occurs.

In the time division multiplex communication type still image transmission device according to the present invention, an address code generator and a modulo 2 (
modulo 2) adder (exclusive OR circuit) is installed, and the address code of the designated line is transmitted before the transmitter starts transmitting image data.

Next, the same address code is continuously generated, the image data and the address code are added modulo 2 in a modulo 2 adder, and the coded code is transmitted.

The receiving side is equipped with the same address code generator, modulo 2 adder, and address detector as the sending side.

An address detector detects the first address code sent from the received data.

Next, the address code generator continuously generates the same address code as the detected specified line.

This address code and encoded image data are added and decoded by a modulo 2 adder.

Then, the decoded image data is sent to the still image transmission device receiving section of the specified line.

With such a circuit configuration, the image data cannot be decoded on the receiving side unless the address code generators on the sending side and the receiving side generate address codes of the same line.

Therefore, even if image data is sent to an incorrectly connected receiver, still images cannot be reproduced.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows the transmitting side of the present invention, where input terminal a receives image data from the transmitting section of the still image transmitting device, and input terminal a receives a control signal (transmission start signal) from the transmitting section of the still image transmitting device. ), a control signal for line selection is applied to input terminals c to d, a clock pulse and a timing pulse from a modem etc. are applied to input terminal e, and an address code is added and encoded from output terminal f. image data is obtained.

Circuits 1, 2, and 3 are each 8-bit parallel input/serial output shift registers, and generate a continuous code of 24 bits as a whole.

The address code generator 4 converts it into a 4-bit BCD code in response to a line selection control signal from input terminals c-d.

The number of line inputs in this embodiment is nine, and the input terminal c is the selection input for the line "1./", or the input terminal d is the selection input for the line "1./".
9// selection input is shown.

Lines 2 to 8 in between are omitted.

The preliminary code setting circuit 5 can freely combine 16-bit codes.

FIG. 3 shows a configuration diagram of the address code described above.

In FIG. 3, codes C-1 and C-2 are address codes of 4 bits each representing a selected line, and the same code is sent twice (8 bits).

Codes C-3 and C-4 are each 8-bit spare codes.

The timing pulse generation circuit 12 receives an external clock pulse or a timing pulse from an input terminal e.

The image data passes through the system indicated by the thick line.

Address code and one of lines 1 to 9 of generator 4
When one line is selected and a transmission request is made, the same transmission request is simultaneously input to the transmission section of the still image transmission device, a transmission start timing signal is input to the input terminal, and the control circuit 6 sends the shift register 1, 2, 3. outputs a timing signal that allows shifting.

A prohibition signal is sent to the gate circuit 7.

The address code is serially output from the shift register and input to the terminal 101 of the modulo 2 adder (exclusive OR circuit) 8.

At this time, the gate circuit 7 is disabled and the terminal 102 of the modulo-2 adder 8 is at level 0, so the address code is sent to the gate 9 with the same polarity.

When 24 bits of address code are sent in one cycle,
The gate inhibition of the gate 7 is canceled by the control circuit 6.

Image data from input terminal a is input from gate circuit 7 to input terminal 102 of modulo 2 adder 8 .

Address codes are continuously generated at the terminal 101.

The modulo 2 adder 8 converts the image data and address code into 1+1=0°0+0=0.1+0=1.0+1=1
Image data is encoded by addition according to the law of modulo-2 addition, which is said to be .

The gate circuit 9 is a circuit for punching out frame synchronization pulses, etc. for reproducing this image data on the receiving side.The gate circuit 10 punches out the position where the frame synchronization pulse etc. is inserted using the timing signal from the circuit 12. Insert a frame synchronization pulse, etc.

The circuit 11 is an etch-triggered D-type flip-flop, and the image data encoded here and further inserted with a frame synchronization pulse etc. is sent to an external modem or its interface circuit in accordance with the phase of the clock pulse from the circuit 12. do.

Figure 2 shows the receiving side of the present invention, where image data reproduced by a modem is applied to the input terminal g, external clock pulses or timing pulses from an external modem, etc. are applied to the input terminal g, and the output is Decoded image data is output from terminals j and k.

Circuits 21 to 23 are serial input/8-bit parallel output shift registers that convert the address code (FIG. 3) transmitted at the beginning of the image data into 24-bit parallel data.

Shift register 22.23 with spare coat 13, C
-4 is parallel-converted and sent to the preliminary code detection circuit 24.

This circuit releases the gate circuit 28 that detects the preliminary code.

The shift register 21 parallelly converts the address codes C-1 and C-2 of the two consecutive lines into 8 bits.

Comparison circuit 25 compares the first 4 bits and the latter 4 bits, and if they match, gate circuit 27 is released.

The address code detection circuit 26 receives the parallel 4-bit address code from the shift register 21 and outputs it to line 1.
Decoding from to line 9.

Next, the decoded address is checked by the gate circuit 27 against an address code match, and by the gate circuit 28 against a preliminary code, and then sent to the gate circuit 28 as a final output. 3
3 and the control circuit 34.

The address code generation circuit 29 is the circuit 1, 2, 3 of FIG.
, 4, and 5, and when it receives a detected address and a control signal from the circuit 34, it continuously generates the same address code as that on the transmitting side.

This output is input to the input terminal 103 of the modulo-2 adder 30.

On the other hand, image data passes through the system indicated by the thick line in FIG.

Image data is input from input terminal g to shift register 21.
is input to the input terminal 104 of the modulo-2 adder 30.

The modulo 2 adder 30 converts the address code and encoded image data into 1+1=0.0+0 in the same way as on the sending side.
Perform modulo 2 addition, which is said to be =0.1+0=1.0+1=1.

When modulo 2 addition is performed twice on the transmitting side and the receiving side as described above, the image data is decoded to the original image data.

The clock pulse generation circuit 35 receives a clock pulse or a dimming pulse from an input terminal and supplies clock pulses to the shift registers 21 to 23, the address code generation circuit 29, and the flip-flop circuit 31.

The decoded image data is phase-aligned with the clock pulse by an edge-triggered D-type flip-flop 31 and input to the gate circuit 31 .

When the gate circuit 32 detects an address from the control circuit 34, it is released and allows the image data to pass through until the end of the image data.

Next, the image data switching circuit 33 selects and transmits the image to the receiving section of the still image transmission device of the line corresponding to the transmitting side.

Upon receiving the line address detected by the control circuit 34 and the control signal from each receiving section, the gate circuit 32 is released during the image signal reception period.

When the line address is detected, shift register 21~
23 is disabled.

It has functions such as generating an address code generator 29 during the image signal reception period.

As explained above, the present invention installs the same address generation circuit on the transmitting side and the receiving side of a time division multiplexing still image transmission device, and after transmitting a specified address code, image data is generated using this address code as 1+1= 0.0+0=0.1
Modulo 2 addition, which is said to be +0=1.0+1=1, is performed and encoded.

After detecting this address code, the receiving side continuously generates the same address code and decodes the image data by performing modulo 2 addition in the same way as the transmitting side.

Therefore, even if the receiving side mistakenly detects the address code and connects the image data circuit to the receiving section of the incompatible line, the address codes do not match and the image data cannot be decoded, resulting in the inability to receive a still image. This has the effect of maintaining confidentiality.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams of a transmitting side and a receiving side, respectively, of an embodiment of the present invention, and FIG. 3 shows an example of an address code. 1.2,3...Shift register, 4...
° Address [code generation circuit, 5... code setting circuit, 6... control circuit, 7, 9, 1
0...Gate circuit, 8...Modulo 2
Adder, 11... Edge trigger D type flop circuit, 12... Clock pulse generation circuit,
21, 22, 23...Shift register, 24
--- Code detection circuit, 25-- Address code comparison circuit, 26-- Address code detection circuit, 27, 28, 32, gate circuit, 29
...-Address code generation circuit, 30...
・Modulo 2 adder, 31...Edge trigger D type flip-flop, 33...Switching circuit, 34...Control circuit, 35...Clock pulse generation circuit.

Claims (1)

[Claims] 1 On the transmitting side, multiple image signals are selectively input, the selected image signals are converted to digital image signals, and written to the image memory on the transmitting side at a speed corresponding to the television speed, and the transmission speed is adjusted to the transmission speed of the transmission line. The digital image signal is read out at a speed that corresponds to the transmission speed of the transmission line, and is selectively sent to multiple receivers in a time-sharing manner via a common transmission line. In a still image transmission device that writes data into an image memory on a receiving side, reads it out at a speed corresponding to a television speed, and converts it into an image signal, the sending side specifies one of a plurality of receiving sides to which the image signal is to be sent. comprising means for generating an address code, and logic means for calculating an exclusive OR between the address code and the transmitted digital image signal,
This exclusive ORed signal is transmitted to a common transmission line instead of a digital image signal, and each of the plurality of receiving sides uses the same address code as the address code specified on the transmitting side corresponding to each receiving side. and logical means for calculating an exclusive OR between the code and the transmitted signal, and writing the exclusive OR signal into the image memory of the receiving side. A time division multiplex communication still image transmission device characterized by: