JPS5810912A - Phase shifter - Google Patents

Abstract

PURPOSE:To increase the varying range for a phase control and to improve the linearity, by synthesizing an output of the 1st frequency multiplier via a 2-branch circuit and a phase shift means and an output of the 2nd multiplier multiplying the output of the branch circuit and connected in parallel with said circuits, with a multiplier and passing through only a specific frequency with a filter. CONSTITUTION:A signal applied to an input terminal 4 is branched into two; one is applied to a phase shift circuit 22 and subjected to a phase shift of theta=k vC with a control voltage vC from a terminal 5. This signal is multiplied by N for the frequency with a frequency N-multiplier 23. Another output signal of a signal branch circuit 21 is applied to frequency (N-1)-multiplier 24, where the frequency is multiplied by (N-1). The signal multiplied by N and that multiplied by (N-1) are applied to a multiplier 25 for multiplication and outputted via a band-pass filter 26. This output signal has a value of N-multiplication to the phase shift theta of the phase circuit 22.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a phase shifter for phase control used in various communication devices.

Conventionally, a typical example of the use of this type of phase shifter is a clock regeneration device for a Gust signal having a prefix word suitable for clock regeneration at the beginning. This clock recovery device is constructed as shown in the block diagram of FIG. In this figure, 1 is a received modulated wave input terminal, 2 is a sample and hold signal input terminal, 3 is a reproduced clock output terminal, 11 is a clock component extraction circuit, 12 is a phase comparison circuit, 13 is a Sanzor hold circuit, and 14 is a clock An oscillation circuit that oscillates at a frequency approximately equal to the
15 is a phase shifter. When a received input modulated wave is applied to the terminal l, a clock component is extracted from the input modulated wave in the clock component extraction circuit 11. A phase comparison circuit 12 compares the phase difference between this clock component and the output of the oscillation circuit 14.

The output corresponding to the phase difference is the sample hold circuit 13.
added to. This added input is integrated in the sample-and-hold circuit 13 to improve the signal-to-noise power ratio (SA), and is also applied to the sample-and-hold pulse applied to the multi-terminal 2 from the outside. The sample will be held a little while ago. This sampled and held voltage is applied to the phase shifter 15 to shift the phase of the input signal applied from the oscillator 14, and then guided to the terminal 3 as a reproduced signal.

To explain the above operation with reference to the time chart in FIG. 2, the waveform (,) is the output of the oscillation circuit 14 and the received signal extracted by the clock component extraction circuit 11, and the phase error between the lock and the output is 08. It shows that the condition is maintained. (b)
is the output signal of the phase comparator 12, and kdθ. A voltage of (kd is the detection sensitivity of the phase comparator) is generated as an output. (c) shows the state in which the sample and hold circuit 13 integrates the outputs given from the nine phase comparators 12. The integrated value near the peak is sampled and held by the sample and hold pulse supplied from the outside (d). (e) shows the voltage sampled and held by the sample and hold pulse in (d) above. This voltage is applied to phase shifter 15 to control the phase of the clock applied to the input. +V here
j is a control voltage for the clock of the preceding burst signal. The control voltage v0 obtained in this way shifts the phase of the first phase shifter 15, while also controlling the phase of the output signal of the first oscillator 14 (not shown in the figure) so that it is synchronized with the received signal clock. A clock with phase is recovered. Generally, the phase difference between the received signal clock and the transmitter 14 is uniformly distributed within ±π, so the phase variable range of the single phase shifter 15 must be at least ±π. Since the phase shifter to be used is composed of a reactance element, its phase variable range is a maximum of 90 degrees, and it is difficult to obtain a large variable range. Another drawback is that linearity compensation for one-phase control characteristics cannot be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase shifter that eliminates the above-mentioned conventional drawbacks, has a wide variable range for single-phase control, and has good linearity.

According to the present invention, there is a signal branching circuit that branches an input signal into two, and a signal branching circuit that receives the output of one of the signal branching circuits.

a first frequency multiplier that multiplies the frequency of the output of the phase shifter by N (N is a positive integer of 2 or more); and a frequency of the other output of the signal branch circuit. a second frequency multiplier that multiplies N-1, a frequency mixer that frequency mixes the output of the first frequency multiplier and the output of the second frequency multiplier, and the output of the frequency mixer In response to this, a phase shifter consisting of a band-pass F-wave filter that passes only the frequency components of the input signal is obtained.An embodiment of a phase shifter according to the present invention of zero-order nine will be described with reference to the drawings.

FIG. 3 is a block diagram showing the configuration of an embodiment according to the present invention. In this figure, 4 is a signal input terminal, 5 is a control signal input terminal, 6 is a reproduced clock output terminal,
21 is a signal branch circuit, 22 is a phase shift circuit, and 23 is a frequency N.
24 is a frequency (N-1) multiplier, 25 is a multiplier, and 26 is a band F wave generator. Now, assume that the received signal applied to the input terminal 4 is 5(t)=selfωs1. Here, ω8 represents the angular frequency of the input signal. This signal is branched into two by a signal branching circuit 21, one of which is applied to a phase shift circuit 22. The phase shift circuit 22 applies a phase shift of θve to θ= to the input signal by the control voltage vc, when its sensitivity is set to θ. Therefore, the output signal g(t
)teeth.

g(t)=dn (ω3 is 10): θ= to θVc'...-
It is expressed as (1). The frequency of this signal is multiplied by N (N is a positive integer, N≧2) by a frequency N multiplier 23,
th(Nω8t+Nθ).

The other output signal of the signal branch circuit 21 has one frequency (N
-1) applied to the multiplier 24 and multiplied by the image ((N-1
) ω, 1) becomes the signal. Then, the signal multiplied by N and the signal multiplied by (N-1) are multiplied by a multiplier 25 to form an output signal v(t).

v(t)=龜(Nω, t+Nθ)・−((N−x)ω5
1)=-1[ω5((2N-1)ω3 is 10Nθ)-co
s(ω8 is 10Nθ)] ・−・・・・・・・(2) is obtained. This signal is applied to a subsequent band p-wave generator 26, where the (2N-1)ω33rd order is removed.

As a result, the output signal has a phase shift amount that is multiplied by N with respect to the phase shift amount 0 of the phase shift circuit 220. In other words, the required amount of phase shift is θ
. Then, the phase shift range of the phase shift circuit 22 is θ. /N means that it is sufficient. To explain this relationship using the graph of FIG. 4, curve 9 (,) shows the characteristics of the phase shift circuit 22 alone, and curve 1 (b) shows the characteristics of the phase shifter shown in FIG. As can be seen from this, the linearity of the control voltage vs. phase shift characteristic of the phase shift circuit 22 alone is not very good, but it is
By appropriately selecting the multiplication number N of the frequency multiplier 23, it is possible to realize a phase shifter with sufficiently good linearity.

In addition, when the phase shifter of the above embodiment is applied to the above-mentioned clock regeneration device, it is shown in FIG.

The phase shifter 15 is removed and the output of the 9 oscillator 14 and the output of the sample hold circuit 13 are input to the input signal terminal 4 in FIG.
It is easy to understand that this is possible by applying the signals to the control and signal terminals 5, respectively.

Further, in the above embodiment, an electrical control circuit composed of a reactance element or the like is used as the phase shift circuit 22, but the present invention is not limited thereto.

For example, it goes without saying that it may be mechanically controlled. Or depending on the purpose of use.

It is clear that a phase shift circuit with a fixed amount of phase shift that does not variably control the amount of phase shift may also be used.

As is clear from the above description, according to the present invention, the variable range of the phase shift amount is wide and control characteristics with good linearity can be obtained.
It has great effects when applied to signal regeneration circuits to improve their operating performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a clock recovery device using a conventional phase shifter, and FIG. 2 is a block diagram showing an example of the configuration of a clock recovery device using a conventional phase shifter. A time chart for explaining the operation in FIG.
FIG. 3 is a block diagram showing the configuration of an embodiment according to the present invention;
FIG. 4 is a graph for explaining the advantage of phase shift control in the embodiment of FIG. 3. In the figure, 21 is a signal branch circuit, 22 is a phase shift circuit, 2
3 is a frequency N multiplier, 24 is a frequency (N-1) multiplier,
25 is a multiplier, and 26 is a band p-wave unit.
^ ^ to U+
cs(1)′+X

Claims (1)

[Claims] 1. A signal branch circuit that branches a human signal into two, a phase shifter that receives the output of one of the signal branchers and shifts its phase, and a frequency of the output of the phase shifter that is N. a first frequency multiplier that multiplies (N is a positive integer of 2 or more); and a second frequency multiplier that multiplies the frequency of the other output of the signal branching circuit by N-1. a frequency mixer that frequency-mixes the output of the first frequency multiplier and the output of the second frequency multiplier; and a bandpass F-wave filter that receives the output of the frequency mixer and passes only the frequency components of the input signal.