JP2876847B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a phase locked loop circuit .
In particular, a complex sample sequence that samples a complex sine wave signal
Input signals and convert them into complex signal components (real and imaginary parts)
Phase synchronization circuit that outputs a phase-synchronized complex sample sequence signal
About the road .

[0002]

2. Description of the Related Art As shown in FIG. 3 , a conventional phase locked loop circuit (hereinafter referred to as a PLL circuit) comprises a mixer 1, a low-pass filter (LPF) 2, and a voltage controlled oscillator (VCO) 3, which are phase comparators. . Although the conventional PLL circuit has a good phase tracking function in the synchronous state,
If the frequency error in the initial stage is large, it takes a long time to pull in the synchronization. Now input signal νi
(T), when the output signal νo of the VCO 3 is expressed by the equations (1) and (2), the output signal νe (t) of the mixer 1 is expressed by the equation (3).

[0003] νi (t) = sin (ωi t + θi) ... (1) νo = cos (ωot + θo) ... (2) νe (t) = νo · νi (t) = 1/2 [{sin (ωi-ωo ) T + (θi−θo)｝ + {sin (ωi + ωo) t + (θi + θo)}] (3) In the output of the low-pass filter 2, sin (ωi−ωo) t
Is output. Therefore, in order to achieve the phase synchronization state, first, ω
It is necessary to set i−ωo = 0. However, when the frequency is outside the pull-in range of the frequency of the PLL circuit, the operation of phase synchronization cannot be started.

[0004]

Since the conventional phase locked loop circuit does not have a pull-in function for quickly setting the initial frequency difference to zero, there is a drawback that the phase lock pull-in time becomes long.

[0005]

SUMMARY OF THE INVENTION In order to solve the above problem, a phase locked loop circuit of the present invention converts a complex sine wave signal to a sampled signal.
Input the complex sample sequence signal
Phase synchronization to obtain an output signal synchronized with the phase of the input signal every time
A circuit for receiving the complex sample sequence signal and
And a first limiter for limiting the first limiter to a constant value.
The output signal is input and the complex of the output signal of the phase locked loop is
A first complex that performs complex multiplication with the value of the sample sequence signal
A multiplier and an unnecessary circuit from the output signal of the first complex multiplier.
A loop filter for filtering a wave number component;
1 sample delay of the output signal of the filter and the complex sample sequence signal
Second complex that performs complex multiplication with the output signal of the delay unit
A multiplier and an output of the second complex multiplier,
A second limiter for limiting the value of the second limiter to a constant value;
An output is input to the delay unit and the phase synchronization circuit is
Is output as an output signal .

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a functional explanatory diagram showing the operation of the present embodiment. Of Figure 1 Li
The input signal to the mixer 5 is an orthogonal two-series complex sine wave signal.
Signal is a complex sample sequence signal obtained by sampling
You. Then, in the present real 施例This complex sample sequence signal input
Limiters 5, 6 that limit the amplitude to a constant value and complex multiplication
Complex multiplier 10 to perform, 1 2, the output signal of the complex multiplier 10
The frequency of the difference between the input signal and the frequency to be synchronized is filtered.
A loop filter 11, 1 San complex sample sequence signal to
One sample delay unit 13 for pull delay , complex sample sequence
It comprises a complex conjugator 14 for taking the complex conjugate of the signal .
Next, the operation of FIG. 1 will be described. The input of limiter 5 is
Sample signal is input and the amplitude is normalized to the specified value 1.
You. The sampling circuit is directly related to the present invention.
1 are omitted from FIG. Next
Next, the function of the complex multiplier will be described. In general, Limi
The complex sample sequence signal passed through the transmitter 5 is x (t) + jy
(T). Here, t is t = nT (n = 0,
, T are sampling periods). This result
As a result , the complex signal is converted into the form of equation (4).

X (t) + ji (t) = ^{ejθ (t)} (4) where θ (t) is the sample position of the complex sample sequence signal.
Phase. It complex multiplier (4) of the two represented by the formula complex sample sequence signal ^{e jθ1 (t), e jθ2} (t)
Multiply each. As a result, equation (5) is obtained.

E ^{jθ1 (t)} · e ^{jθ2 (t)} = e ^{j {θ1 (t) + θ2 (t)}} (5)

That is, a complex multiplier is composed of two complex samples.
It has the function of adding each phase of the pull train signal. Of the present invention
The complex multiplier 10 uses a complex conjugator 14 to perform a phase synchronization circuit.
Conjugate signal obtained by complex conjugate of the output signal of the path and limiter 5
The output is multiplied. In this case, for example, a complex signal
complex conjugate signal ^e jθ ^(t) is the ^{e -jθ (t)}
Therefore, the phase of the output signal of the complex multiplier 10 is
Phase difference between the phase of the force signal and the phase of the output signal of the phase locked loop
Becomes Next, transmission of the loop filter 11 in FIG.
The function is given by equation (6).

[0011] Here, τ is a time constant of the filter.

Now, the input signal Ve of the loop filter 11
(T) is represented by equation (7) .

Ve (t) = ej ^{(ωet + θe)} (7) Here, θe indicates a phase delay.

The transfer function of the loop filter 11 in equation (6)
, The output signal V′e (t) of the loop filter 11 is expressed by equation (8).

[0015]

As shown by the equation (8), only a phase delay is generated in which the arc becomes tan ωeτ. Less than
The signal of the complex sample sequence in the configuration of FIG.
The operation for the phase is performed individually using the Z-transform as follows.
A description will be given for each road. Here, Θi (z) and Θo (z) are input
Each phase θi (t), θo (t) of the output signal is z-transformed
Things. As described above, the output signal of the complex multiplier 10 is
The phase 号 e (z) of the signal is Θe (z) = Θi (z) −Θo
(Z). Further, assuming that ωe is constant , the loop filter 11 has a constant phase lag ( −tan ⁻¹ ωeτ) component as shown in Expression (8).
Therefore, the Z transformation is -tan ^-1 ωeτ / (1-Z ^-1 )
Becomes Further, a multiplier 12, a one-sample delay unit 13,
The transfer function of the circuit constituted by the limiter 6 is obtained by Z conversion.
1 / (1−Z ⁻¹ ). The above has been described for each individual circuit.
The transfer function of the Z-transform is summarized as shown in FIG. Obedience
Therefore, from FIG. 2, the phase Θo (z) of the output signal is

[0017]

## EQU1 ## Now the input signal is expressed by equation (10)
Then, θi (t) = ωit + φi (10)

The n-th sample value is θi (n) = ωiTn + φi (11).

When the Z transformation of the equation (11) is performed,

## EQU2 ## Substituting equation (12) into equation (9)
Then, a Z-transform of the phase of the output sample sequence is obtained. Next
And the n-th sample value of the output signal phase as
When the inverse Z-transform of （o (z) is performed and θo ( n ) is calculated, Equation (14) is obtained.

Θo (z) = Σθo (n) Z− ⁿ (13)

[0023]

Usually, since the sampling number n is large, the last term quickly converges to 0,

Θo (n) → ωiTn + φi− ωiT ⁻ tan−1ωeτ (15)

[0026] to become, but the fact that this is ωe becomes 0
Therefore , the third term of the equation (15) also converges to 0 and

Θo (n) → ωiTn + φi− ωiT (16)

The [0028]. Here, equations (11) and (16)
By comparison, the phase given by equation (16) is
The phase is delayed by (-ωiT) from the phase given by the equation.
ing. Normally, this phase delay depends on the sampling frequency.
Sufficiently higher than force frequency, sufficient sampling period
It becomes small and can be ignored. As a result, the input signal
The phase coincides with the phase of the output signal, and phase synchronization is correctly established. As described above, according to the present invention, phase synchronization is correctly established even when there is an initial frequency error.

[0029]

As described above, according to the present invention, the following effects can be realized by performing digital arithmetic processing with a limiter, a complex multiplier, and a loop filter.

(1) It is possible to realize a PLL circuit that correctly performs synchronization even if there is an initial frequency error without using a VCO .

(2) It is possible to realize a narrow band PLL circuit that operates even under a low C / N condition.

(3) The present circuit can be applied to a communication field having a low C / N and many instantaneous interruptions such as mobile satellite communication.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

FIG. 2 is an explanatory diagram of functions of the embodiment.

FIG. 3 is a block diagram of a conventional phase locked loop circuit.

[Explanation of symbols]

5,6 Limiter 10,12 Complex multiplier 11 Loop filter 13 1-sample delay unit 14 Complex conjugate unit

Claims (1)

(57) [Claims] 1. A complex sampled complex sine wave signal.
Input the sample sequence signal and place the input signal for each complex component.
In a phase-locked loop that obtains an output signal synchronized with the phase,
Input a complex sample sequence signal and limit the amplitude to a constant value
A first limiter and an output signal of the first limiter are input.
Of the complex sample sequence signal of the output signal of the phase locked loop
A first complex multiplier for performing complex multiplication with the value,
Filter unnecessary frequency components from the output signal of the complex multiplier 1
A loop filter, and an output signal of the loop filter.
The output of the delay unit that delays the complex sample sequence signal by one sample
A second complex multiplier for performing complex multiplication with a force signal;
Input the output of a complex multiplier of 2 and limit the amplitude to a constant value
A second limiter and an output of the second limiter to the delay unit
And as an output signal of the phase locked loop
A phase-locked loop characterized by outputting .