JPS58106591A - Crt display circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is suitable for application to personal computers, etc.
This invention relates to an RT display circuit. First, a conventional CR, T display circuit will be explained with reference to FIG. (1) is a monitor receiver, and has a CRT (2). (5) is a video control circuit, and the red, green and blue signals and horizontal and vertical synchronization signals NT8 from this video control circuit (5)
A local subcarrier signal for color encoding of frequency fsc (3,58 MHz) from a local subcarrier oscillator (4) is supplied to the C encoder (3).
)K, and the resulting high-frequency composite television signal is supplied to the monitor receiver (1).

Although (7) is a character generator as a pattern generator, it may also be a graphic generator. The character signal as a unit pattern signal from the character generator (7) is supplied to the video control circuit (5) through a parallel-to-serial conversion circuit (shift register) (6).

(8) is a video memory, which is a refresh type RA
M is used. The unit pattern code signal from the video RAM (81) is supplied to the above-mentioned character generator (7).

(13) is a central processing unit to which a main address bus AB and a main data bus DB are connected. An address signal from the address bus AB is supplied to the multiplexer (video memory +8) K via the address bus AB.

Further, 00) is a bus drive circuit, and the data bus D
B, and the above-mentioned video and audio control circuits (
5), character generator (7) and video memory (8)
It is connected to the.

(1m) is a CRT control circuit (CRTC) from which the display timing signal DT and cursor display signal C
D, a horizontal synchronizing signal H8 and a vertical synchronizing signal S are supplied to the video control circuit (51).

A color pit signal CB is also supplied to the video control circuit (5). C) The tT control circuit 0υ is connected to the multiplexer (
9) to be supplied with the memory address signal MA, and connected to the character generator (7) K via the raster address RAB so as to be supplied with the raster address signal RA. ing. This C
The RT control circuit (Ill) is also connected to the main address bus AB and main data bus DB.

(14a) and (14b) are dot clock oscillators having different clock frequencies f1 and f2, respectively, and their oscillation outputs are supplied to the divider Q'll (with the frequency division ratio) via the changeover switch f151. It is made to be done.

The dot clock signal DK (frequency is fdk) supplied to the branch divider 021 button is supplied to the branch divider CL21 and also to the parallel-to-serial conversion circuit (6). From the divider 02, a character clock signal (frequency is fck) C is output as a unit pattern clock signal.
K is obtained and supplied to the CRT control circuit.

In this CRT control circuit (Iυ), this character clock signal CK is frequency-divided, for example, by -4 to obtain a horizontal synchronizing signal H8.
In the control circuit 0υ, each other signal also has this character.
It is created based on the clock signal CK.

Assuming that a dot clock signal with a clock frequency f1 of 7 MHz is obtained from the don't clock generator (14a), this is divided by a page, for example 1, by a divider α3 to obtain a frequency f1. A character clock signal CK with k of 1 MHz is obtained, which is supplied to C) the LT control circuit circle, where a horizontal synchronization signal with a frequency rH of 15.6 kI-1z is produced.

For example, the number of characters displayed in the horizontal direction on the screen of CR1't2) is assumed to be 40 characters. Also, the number of dots in one character is, for example, 7 in the horizontal direction. 9 in the vertical direction. Horizontal period approximately 64μse
For example, set the display period for displaying characters in c to 40
Take μsec K. In this way, the period of one character is 1 μs
ec, and the frequency of the character clock signal is the above-mentioned IMHz. In this way, the frequency fdk of the dot clock signal DK becomes 7 MHz.

If you want to change the number of characters displayed in the horizontal direction of CR'l' (2) or the number of dots per character, use the changeover switch (15) mentioned above to switch the clock oscillator (14b).
). For example, the clock frequency f2 is g
MHz and the number of horizontal dots per character is 7.
Consider changing from 8 to 8. In this case, the frequency division ratio of the frequency divider a2I remains -, and the division ratio when dividing the character clock frequency fck to obtain the horizontal synchronization signal is fixed at -4. If a dot clock signal with a frequency f 2 =3 MHz is used, the frequency of the horizontal synchronizing signal will be 17.9 kHz, which will cause problems in screen display.

In view of these points, the present invention is aimed at increasing the number of unit patterns displayed on a CRT screen, such as the number of characters displayed in the horizontal direction, the number of graphics displayed, or the number of dots per character in the horizontal direction, the number of dots per one graphic, etc. The object of the present invention is to propose a CRT control circuit in which the frequency shift of the synchronizing signal does not occur even if the number of dots per unit pattern in the horizontal direction is changed.

The present invention provides a video control circuit that supplies a video signal and a video synchronization signal to a CRT, a pattern generator that supplies a unit pattern signal to the video control circuit via a parallel-to-serial conversion circuit, and a unit pattern signal that is supplied to the pattern generator. a video memory that provides a code signal; a CRT control circuit that controls the video memory and the pattern generator and provides display timing and synchronization signals to the video control circuit;
C) A tT display circuit that has a divider that supplies a unit pattern clock signal to a CRT control circuit, and a dot clock generator that supplies a dot clock signal to this frequency divider and a parallel-to-serial conversion circuit. The dot clock generator is configured with a PLL circuit that includes a comparator that compares the phases of the signal and the horizontal synchronization signal from the CR'l'' control circuit, and a variable oscillator that is controlled based on the comparison output from this comparator. In addition, the frequency divider described above is configured by a programmable frequency divider.

An embodiment of the present invention will be described below in detail with reference to FIG. 2. In FIG. 2, parts corresponding to those in FIG.

041 is a dot clock generator, hereinafter referred to as the oscillation frequency f. is set to four times the subcarrier frequency fsc.

Then, this reference oscillation signal is passed through a divider αη with a frequency division ratio of d.
The horizontal frequency fH is 15.74 kHz.
Obtain the horizontal frequency signal, supply it to the comparator a, and compare the phase with the horizontal synchronizing signal J (S) from the CRT control circuit αυ. Supply to the voltage controlled oscillator (20) to control its oscillation frequency.Variable oscillator (a)
A dot clock signal DK having a frequency fdk of, for example, 7 MHz is obtained from the dot clock signal DK, which is supplied to the programmable frequency divider and also to the parallel-to-serial conversion circuit (6).

For example, if the number of dots in the horizontal direction of one character is 7, the frequency division ratio of the frequency divider 0 is selected to be 7. Variable oscillator (20
A dot clock signal with a dot clock frequency fdk cuff MHz is obtained from the dot clock frequency fdk, and this is supplied to the frequency divider 0z, so that a character clock signal CK of I MHz is obtained on the output side, which is used by the CRT control circuit (1υ supplied to

If the number of dots in the horizontal direction of one character is to be changed from 7 to 8, the frequency division ratio of the frequency divider α2 may be changed from 1 to -8. In this way, a dot clock signal with a dot clock frequency fdk of f3 Ml-4z is obtained from the variable oscillator QQ, and this is supplied to the frequency divider (12+ and divided into i, so that the character clock signal C
K frequency f. k is still lM)-1z and is constant. Therefore, the frequency fH of the horizontal synchronizing signal is set to the negative value of this, and becomes a constant 15.74 kHz.

In this example, the local subcarrier oscillator (4) is composed of a reference oscillator 4161 and a divider (17) with a frequency division ratio of - to which the reference oscillation signal is supplied from the reference oscillator 4161.
A local subcarrier signal with a frequency fsc of 3.58 MHz is obtained and supplied to the encoder (3).

According to the present invention described above, even if the number of dots in the horizontal direction of the unit pattern or the number of characters in the horizontal direction on the screen of CRi' is changed, the frequency of the synchronization signal obtained from the CRT control circuit does not change.

In addition, since the local subcarrier signal supplied to the encoder is based on a reference oscillator from a common reference oscillator that constitutes the dot clock generator, the dots and colors of the unit pattern can be synchronized in phase and displayed on the CRT. Color images become easier to see.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional CRT display circuit, and FIG. 2 is a block diagram showing an embodiment of the present invention. (1) is a monitor receiver, (2) is a CRT, (3) is an encoder, (5) is a video control circuit, (6) is a parallel-serial conversion circuit, (7) is a pattern generator, and (8) is Video memory, (9) is a multiplexer, aυ is C)tT control circuit, (121 is a frequency divider, 0J is a central processing unit, +14
1 is the dot clock generator, σ6) is the reference oscillator, αD
is a splitter, ``Kake'' is a comparator, ``αj'' is a low-pass filter, and ``Kan'' is a variable oscillator. Figure 1 Figure 2

Claims (1)

[Claims] A video control circuit that supplies a video signal and a synchronization signal to a CRT, a pattern generator that supplies a unit pattern signal to the video control circuit via a parallel-to-serial conversion circuit, and a unit pattern code signal that supplies the pattern generator. a CRT control circuit that controls the video memory and the pattern generator and supplies a display timing signal and a synchronization signal to the video control circuit;
In a CRT display circuit that includes a divider that supplies a unit pattern clock signal to an RT control circuit, and a dot clock generator that supplies a dot clock signal to the frequency divider and the parallel-to-serial conversion circuit, The dot clock generator is configured with a PLL circuit including a comparator that compares the phases of horizontal synchronizing signals from the CRT control circuit, and a variable oscillator that is controlled based on the comparison output from the comparator. . A CRT display circuit, characterized in that the frequency divider is a programmable frequency divider.