JPS58105646A - Subcarrier signal generating device for stereo tuner - Google Patents

Abstract

PURPOSE:To easily design a filter, by eliminating higher harmonic components generated in a PLL circuit. CONSTITUTION:A VCO5 oscillates at 304kHz and an output (b) from the VCO5 is applied to trigger inputs of D-FFs 9, 10 in common. The D-FFs 9, 10 constitute what is called a ring counter. An output (c) from an output terminal Q of the D-FF9 is divided by a 1/2 divider 6 and the output (e) is applied to an adder 11 and an exclusive OR gate 12 to be used as a level coincidence detector. An output (d) from an output terminal Q of the D-FF10 is applied to the other input terminal of the gate 12 and a level coincidence detecting output (f) is applied to the other input terminal of the adder 11. The added output (g) is applied to a BPF7 and a sine wave subcarrier signal (h) outputted from the BPF7 is converted into a 38kHz square wave (i) by a level comparator 8. The wave (i) is converted into a 19kHz square wave (j) by a 1/2 frequency divider 1, and then compared in phase with a stereo pilot signal (a) in a phase comparator 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a subcarrier signal generation device in a stereo tuner, and more particularly to a device for generating a sinusoidal subcarrier signal synchronized with a stereo pilot signal in an FM stereo tuner.

The MPX (multiplex) intuner in the FM stereo tuner generates a 38KH2 sine wave subcarrier signal and multiplies it by the composite signal in order to demodulate the subsignal in the stereo composite signal. In order to generate a 38KHz subcarrier signal synchronized with this
It uses an LL (phase locked loop) circuit.

That is, the pilot signal (a) is phase-compared with the 19KHz signal (f) from the 1/2 frequency divider 2 in the phase comparator 1, and the comparison output is passed through the LPF 3 and the DC amplifier 4 to the VCO (voltage l1lIa type oscillator). )5. This VCO 5 generates a 76KHz trigger pulse (b), which is converted into a 38KHz square wave (C) by the 1/2 frequency divider 6.
becomes. This square wave signal @ (C) is converted into BPF (or LPF
)7 to input the 38KH2 sine wave subcarrier signal (
d). This signal (d>) is also applied to the level comparator 8 and converted into an in-phase rectangular wave signal (e), which is then converted into a 19 KHz rectangular wave signal (e) by the 1/2 frequency divider 2.
f). In this way, a sinusoidal subcarrier signal synchronized with the stereo pilot signal (a) in the composite signal is obtained.

2(a) to 1(f) show waveforms of signals (a) to (f) of each part of the circuit of FIG. 1, respectively.

Here, the 38KHz rectangular wave input to BPF7 is 11 (t') = (4/7r) Sin ωs
t+ (4/3π)Sin 3ωst+ (4157r
) Sin 5ωst+・・・−・・・・・・・・・・・・
...(1) It is expressed as. Note that ωS is the angular frequency of the subcarrier signal. The waveform shown by this equation (1) is shown in Figure 3 (a).
The frequency spectrum is as shown in FIG. 3(b). In other words, 3 times, 5 times...
The odd harmonic is 1/3.115. of the fundamental wave.
. . . Therefore, the transmission characteristics of the BPF (or LPF) 7 need to be as shown in FIG. As a result, the number of filter elements increases and the gain begins to decrease very close to 38KH2, so there is a drawback that the level of the 38KH2 sine wave changes due to temperature drift and the like.

An object of the present invention is to provide a subcarrier signal generator that eliminates 3rd and 5th harmonic components included in a 38KH2 rectangular wave signal, facilitates filter design, and eliminates level fluctuations in the 38KH2 signal. It is.

A subcarrier signal generation device in a stereo tuner according to the present invention includes means for generating a rectangular wave signal synchronized with a stereo pilot signal, having a phase difference of 90 degrees from each other, and having a fundamental wave four times the pilot signal frequency; A means for frequency-dividing one of the wave signals to 1772, a level coincidence detecting means for manually detecting the frequency-divided output and the other of the rectangular wave signals, and a desired comparison (A /'7 + 1 > means for caulking and combining;
The present invention is characterized in that it includes extraction means for extracting the fundamental wave component of the Korean output and outputting it as a subcarrier signal.

The present invention will be explained below with reference to the drawings.

FIG. 5 is a circuit diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 1 are designated by the same symbols. Regarding the differences from the conventional example shown in Figure 1, the VCO5 has a frequency of 304KHz.
This output (b) is commonly applied to the trigger inputs of D-FFs (delayed flip-flops) 9 and 10. The Q output (c) of D-FF9 is D-
It serves as a data input for FF 10, and the Q output (d) of D-FF 10 serves as a data input for D'-FF 9, forming a so-called ring counter configuration. The Q output (C) of the D-FF 9 is frequency-divided by the 1/2 frequency divider 6, and the frequency-divided output (e) is sent to the adder circuit 11 and the exclusive OR gate 12 as a level-number divider. Each of the 15- inputs. Also, the Q output of D-FFIO (d
) is considered to be an outsider's power of gate 12, and this gate 12
The level-number output (f >) is the output of the adder circuit 11. This adder output (g) passes through the BPF (or LPF) 7, becomes a sine wave subcarrier signal (h), and is output from the circuit. At the same time, the level comparator 8 converts it into a 38KHz rectangular wave ((), and the 1/2 frequency divider 2
19KH2 rectangular wave (j>), and the phase is compared with the stereo pilot signal (a) in the phase comparator 1.

6(a) to (j) show the respective waveforms of the signals (a) to (j>) in the circuit of FIG. 5.V
CO5 is <304KH2 (6ωS) as shown in Figure (b).
A ring counter using D-FF9.10 generates trigger pulses with a duty of 50% and a phase difference of 90'' from each other as shown in Figures (C) and (d).
A square wave of KHz (2(2)S, ie, a frequency four times the pilot signal frequency) is obtained. The frequency of this rectangular wave))(C>=6- is divided by 1/2 and the frequency is 38KHz (ωS) as shown in figure (e).
) is obtained, and by inputting this rectangular wave and the output (d) to the level-number hanger 12, the coincidence detection output shown in FIG. 2(f) is obtained.

The frequency division output (e) of the 1/2 frequency divider 6 and the -number output output (f
) at a level ratio of (f7+1):1, a waveform shown in the figure (CI>) is obtained.

This becomes the input of BPF7, and only the fundamental wave component is input to this BPF.
By extracting with PF, a 38 KHz sine wave subcarrier is obtained as shown in Figure (h).

In FIG. 7, the signals of each part of the circuit of FIG. 5 (e >,
Details of the waveforms in (d), (f) and (a) are shown, respectively. Here, 38KH shown in Figure 7
2 square waves (e) as 17+(t) and Surto, i7+(L
)=(4/π) sinωst+(4/3π) sin
3ωst+ <4/ 5 π) sin 5ωst+・
......
Then, 1/2 (t) = (4/27)Sin
2ωs (t −T, □8)+ (4/3π)s
in 6ωs (-King/8)+(415yr)si
n 1 0ωS (t −T/ 8 ) +
=−・・・・・・・・・ (3) It becomes. Note that T indicates one cycle of a 38 KHz rectangular wave. Furthermore, if the -number output (f) is V3 (t), then V3 (t) = (4/π) ((F - 1) sin
ω5t-(<t7+ 1)/3) stn 3ω5t
−((F7+1)15) sin 5ωst+ ((f
7-1) /7) sin
7 ω st + ・・−−′−・ 〕 −・・
−・−(4). Therefore, the signal V+ (t) shown by equations (2) and (4)
Tora (F + 1) : If we add with a level comparison of 1, the addition h(a) will be va (t) = (8/ (t7 + 1) π)・(
sin ωst+ (1/7) sin 7ωst+ (
1,'9) sin gωst+・・・・・・) ・・・
(5) As a result, a signal containing no third and fifth harmonics is obtained.

The frequency spectrum of the output Va(j) of this decoration signal (0) is as shown in Fig. 8(a), so the frequency spectrum of the output Va(j) of this decoration signal (0) is as shown in Fig. 8(b).
It becomes possible to extend the passband characteristic of the BPF 7 to a higher frequency range as shown in FIG.

FIG. 9 is a diagram showing an example of the adder circuit 11, in which differential transistors Q3 and Qa are switched by positive and negative phase rectangular waves of 38 KHz, and differential transistors Qs and Q
s is switched by the positive and negative phase signals of the level-number output signal. Collector output of transistor Q3゜Qs and transistor Q4.

Addition is performed at the collector output of Q6, and one collector output is derived as a decoration output. The decoration composition ratio is
It is determined by the current ratio of the current sources of transistors Q+ and Q2, and is selected as I + /I 2 =F + 1.

FIG. 10 shows an example of an adder circuit including a level-number construction circuit 12, and parts equivalent to those in FIG. 9 are designated by the same reference numerals. Transistors Q3, Qg.

9-Q5 and Q6 are all switched by 38K)-12 square wave positive and negative phase signals, and transistors Qs,
The collector outputs of Qa are connected to differential switch transistors Q7. It serves as a current supply source for Q8 and Qs*Q10. Transistor Q7. Q8 and Q9. QI
O are switched by positive and negative phase signals of 76KH2 square waves, respectively, and transistors Q3, Q7, Q
9 collectors and transistors Q= , Qa , QI
The respective collectors of O are connected in common and output a composite waveform. Note that transistors 05 to Q10 constitute an exclusive OR gate circuit.

Like Soft Earth, according to the present invention, it is possible to cancel odd harmonics such as 3ωS and 5ωS generated within the PLL circuit, so the BPF (
It is now possible to extend the characteristics of the filter (or LPF) to high frequencies, and to make the attenuation characteristics gentler, allowing the design and configuration of the filter to be integrated into the cylinder, and making it possible for changes in the filter characteristics to have no effect on the 38 KHz level. There are benefits to giving.

10-

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional 38KHz subcarrier signal generator, Figure 2 is a signal waveform diagram of each part of the circuit in Figure 1, and Figure 3 is a diagram of the signal waveform of each part of the circuit in Figure 1.
4 and 4 are diagrams explaining the characteristics of the circuit in FIG. 1, and FIG.
The figure is a circuit diagram of an embodiment of the present invention, FIG. 6 is a signal waveform diagram of each part of the circuit of FIG. 5, FIG. 7 is a diagram showing some details of the signal waveform of FIG. 5, and FIG. A diagram explaining the characteristics of the circuit in the diagram,
9 and 10 are diagrams showing specific examples of a portion of the circuit shown in FIG. 5. FIG. Explanation of symbols of main parts 5... VCO 6... 1/2 frequency divider 7.
...BPF 9.10...D-F
F11... Addition circuit 12... Exclusive OR gate for level-number structure output Applicant: Pioneer Co., Ltd. Agent Patent attorney Motohiko Fujimura 11-

Claims (2)

[Claims] (1) Synchronized with stereo pilot signal and 90° to each other
means for generating a rectangular wave signal having a phase difference and a fundamental wave four times the pilot signal frequency; a frequency dividing means for frequency dividing one of the rectangular wave signals to 1/2; and the frequency dividing means. and the other of the rectangular wave signals; means for adding and synthesizing the output of the frequency dividing means and the output of the coincidence detecting means at a desired ratio; 1. A subcarrier signal generating device in a stereo tuner, comprising: extraction means for extracting a fundamental wave component and outputting the extracted fundamental wave component as a subcarrier signal. (2) The subcarrier signal generation device according to claim 1, wherein the desired ratio is (/7+1).