JPS58105594A - Method of producing hybrid integrated circuit device - Google Patents

Method of producing hybrid integrated circuit device

Info

Publication number
JPS58105594A
JPS58105594A JP56204652A JP20465281A JPS58105594A JP S58105594 A JPS58105594 A JP S58105594A JP 56204652 A JP56204652 A JP 56204652A JP 20465281 A JP20465281 A JP 20465281A JP S58105594 A JPS58105594 A JP S58105594A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
solder
circuit device
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56204652A
Other languages
Japanese (ja)
Inventor
正行 片岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP56204652A priority Critical patent/JPS58105594A/en
Publication of JPS58105594A publication Critical patent/JPS58105594A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 この発明は、フェースボンディング用のフラットリード
な備先たモールドタイプの半導体部品を混成集積回路基
板上に半田付けを行うに際し、半田ペーストリノロ一時
に半導体部品のモールド部に7ラツクスを滴下しながら
、半田付けを完rするようにした混成集積回路装置の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides a method for soldering a mold type semiconductor component with a flat lead for face bonding onto a hybrid integrated circuit board. The present invention relates to a method of manufacturing a hybrid integrated circuit device in which soldering is completed while dropping 7 lux onto the surface of the hybrid integrated circuit device.

従来、混成集積回路装置での半導体部品の実装方法では
、裸チップをダイボンド、ワイヤボンドする方法、フリ
ップチップなどのワイヤスボンデイングする方法などが
行われている。
2. Description of the Related Art Conventionally, methods for mounting semiconductor components in a hybrid integrated circuit device include die bonding or wire bonding of bare chips, wire bonding such as flip chip, and the like.

半導体部品1時に、ICが集積度を増して行くと、IC
単体で充分な特性検査が可能でかつ組立、検査での取扱
いが各易なフェースボンディング用のフラットリードを
備えたものが多(用いられてきている。
Semiconductor components 1: As ICs increase in integration, ICs
Many products are being used that are equipped with flat leads for face bonding, which enable sufficient characteristic testing on their own and are easy to assemble and handle during testing.

フラットリードタイプは他の受動、能動のチップ部品と
同時に混成集積回路基板上尺取り付けることができる。
The flat lead type can be mounted on a hybrid integrated circuit board at the same time as other passive and active chip components.

その取付方法は一般に半田付けが多(、中でも、半田ペ
ーストを基板上に印刷後、基板上に仮置きしく以下、プ
レーシングと云う)、半田リフローして半田付けを完了
する方法が多く用いられている。
The mounting method is generally soldering (in particular, a method in which solder paste is printed on the board and then temporarily placed on the board, hereinafter referred to as "placing"), and a method that completes the soldering by reflowing the solder is often used. ing.

ここで、従来の混成集積回路装置の製造方法について図
面に基づき概述する。第1図はフラットリードな備えた
半導体部品を組み立てた混成集積回路基板を示す平面図
であり、混成集積回路基板1上に受動、能動のチップ部
品4と同時にフラントリードを有する半導体部品5を半
田付けしたところを示すものである。
Here, a conventional method for manufacturing a hybrid integrated circuit device will be briefly described with reference to the drawings. FIG. 1 is a plan view showing a hybrid integrated circuit board in which semiconductor components with flat leads are assembled, and semiconductor components 5 with flat leads are soldered onto the hybrid integrated circuit board 1 at the same time as passive and active chip components 4. This shows where it is attached.

この組立工程を第2図ないし第4図を参照して説明する
。まず、第2図に示すように、混成集積回路基板1上の
導体2に第3図a(断面図)、第3図b(平面図)に示
すように、半田ペースト3をメタルマスクなどを使用し
て印刷する。
This assembly process will be explained with reference to FIGS. 2 to 4. First, as shown in FIG. 2, solder paste 3 is applied to the conductor 2 on the hybrid integrated circuit board 1 using a metal mask or the like as shown in FIG. 3a (cross-sectional view) and FIG. 3b (plan view). Use and print.

その後、第4図に示すように、チップ部品4およびフラ
ジ) IJ−ドな備えた半導体部品5をブレーシングす
る。
Thereafter, as shown in FIG. 4, the chip component 4 and the semiconductor component 5 provided with the flange are brazed.

次いで、加熱台(ホットプレート)などに載せて、半田
リフローし、半田付けを完了する。この際、半田ペース
ト3の量が少なすぎると、リードのオープン不良や、半
田付強度が弱い。そのため、半田量を若干多口にコント
ロールするが、第5図に示すように、フラットリード6
のリード間隔が狭い場合、半田ブリッジ7が生じ、電気
的不良が生じ易い。
Next, it is placed on a heating table (hot plate) and the solder is reflowed to complete the soldering. At this time, if the amount of solder paste 3 is too small, leads may fail to open or the soldering strength may be weak. Therefore, the amount of solder is controlled slightly larger, but as shown in Figure 5, the flat lead 6
When the lead spacing is narrow, solder bridges 7 occur, which tends to cause electrical defects.

また、外部への引出端子が多く、多数のフラットリード
な備えるようになると、リード間隔が狭くなり、半田付
けの際に隣接するリード間で半田ブリッジが生じ、組立
歩留りを低下させゐ。
Furthermore, when there are many terminals leading out to the outside and a large number of flat leads are provided, the lead spacing becomes narrower, and solder bridges occur between adjacent leads during soldering, reducing the assembly yield.

さらに、上述の半田ブリッジ7を生ずる原因は半田ペー
スト量が多(、予熱時に隣接するリードパターン上の半
田ペーストの一部が混ざり合い、半田リフローの際でも
、半田ペーストに含まれるフラックスだけでは、フラッ
トリードへ半田をなじませ、かつリード間に存在する半
田を表面張力でそれぞれのリードに戻るには充分である
Furthermore, the cause of the above-mentioned solder bridge 7 is the large amount of solder paste (some of the solder paste on adjacent lead patterns mixes during preheating, and even during solder reflow, the flux contained in the solder paste alone cannot be used). It is sufficient to spread the solder onto the flat leads and to return the solder existing between the leads to the respective leads by surface tension.

逆に半田ペースト量を少なくすると、リードの付着強度
が減少したり、リードと基板導体パターンとのオープン
不良が生じ易い。
On the other hand, if the amount of solder paste is reduced, the adhesion strength of the leads will decrease, and open failures between the leads and the substrate conductor pattern will likely occur.

この発明は、上記従来の欠点を除去するためになされた
もので、混成集積回路基板上に半田ペーストを印刷し、
その上にフラットリードな多数備えたモールドタイプの
半導体部品やその他のチップ部品などを仮付けした後、
半田リフロ一時、フラットリード部品のモールド部にフ
ラックスを滴下しながら半田付けを行うようにして、フ
ラットリード部へもフラックスが付着し、半田ぬれ性が
同上されるとともに、半田なじみがよくなるばかりか、
半田の表面張力を増進させ、リード間での半田ブリッジ
もすべて解消できる混成集積回路装置を提供することを
目的とする。
This invention was made to eliminate the above-mentioned conventional drawbacks, and includes printing solder paste on a hybrid integrated circuit board,
After temporarily attaching mold-type semiconductor components with a large number of flat leads and other chip components,
During solder reflow, soldering is performed while dripping flux onto the molded part of the flat lead component, so that the flux adheres to the flat lead part as well, improving solder wettability and improving solder compatibility.
It is an object of the present invention to provide a hybrid integrated circuit device in which the surface tension of solder is increased and all solder bridges between leads can be eliminated.

以下、この発明の混成集積回路装置の製造方法の実施例
について図面に基づき説明する。第6図はその一実施例
を説明するための断面図であり、この第6図において、
第1図ないし第4図と同一部分には同一符号を付し′〔
述べる。
Embodiments of the method for manufacturing a hybrid integrated circuit device of the present invention will be described below with reference to the drawings. FIG. 6 is a sectional view for explaining one embodiment, and in this FIG. 6,
The same parts as in Figures 1 to 4 are designated by the same reference numerals.
state

このM6図に′Mいて、混成集積回路基板l上にチップ
部品4とフラットリード6の半導体部品5をプレーシン
グして、半田リフロ−する際に、半導体部品5の上方よ
り点滴容器8などを用いて、フラックス9をモールド中
央部に滴下する。
As shown in Fig. M6, when placing the chip component 4 and the semiconductor component 5 of the flat lead 6 on the hybrid integrated circuit board l and reflowing the solder, insert the drip container 8 etc. from above the semiconductor component 5. Using the same method, drop flux 9 onto the center of the mold.

このフラックス9はモールド部より各フラットリード6
へ伝って流れ、フラットリード6と半田3aの表面張力
を増進させ、フラットリード6間の半田ブリッジが全く
生ずることなく、第7図に示すように半田付けを完了す
る。
This flux 9 is applied to each flat lead 6 from the mold part.
The solder 3a increases the surface tension between the flat leads 6 and the solder 3a, and completes the soldering as shown in FIG. 7 without any solder bridging between the flat leads 6.

併せて、この発明の製造方法では、モールド部が半田リ
フロ一時Kかなりの高温零囲気にさらされるのを7ラツ
クスを滴下することにより、モールド部を冷却する作用
が生じ、モールド内部の半導体素子への熱ストレスを軽
減する効果が得られると云う画期的なものである。
In addition, in the manufacturing method of the present invention, the mold part is temporarily exposed to extremely high temperature freezing air during solder reflow by dropping 7 lux to cool the mold part, and the semiconductor element inside the mold is cooled. This is a groundbreaking product that is said to be effective in reducing heat stress.

以上のように、この発明の混成集積回路装置の製造方法
によれば、混成集積回路基板上に半田ペーストを印刷し
、この半田ペースト上にフェースボンディング用のフラ
ットリードを多数備えたモールドタイプの半導体部品を
仮付けし、その後、半田リフローする際に半導体部品の
モールド部にフラックスを滴下しながら半田付けを完了
するようKしたので、フラットリード部へもフラックス
が付着し、半田ぬれ性が向上するとともに、半田なじみ
がよくなり、しかも、半田の表面張力を増進させること
ができ、したがって、リード間での半田ブリッジもすべ
て解消される利点を有する。
As described above, according to the method for manufacturing a hybrid integrated circuit device of the present invention, a solder paste is printed on a hybrid integrated circuit board, and a mold type semiconductor having a large number of flat leads for face bonding is printed on the solder paste. After temporarily attaching the parts, when reflowing the solder, we completed the soldering while dripping flux onto the mold part of the semiconductor part, so the flux also adhered to the flat lead part, improving solder wettability. At the same time, it has the advantage that solder compatibility is improved, and the surface tension of the solder can be increased, so that all solder bridges between leads are eliminated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はフラット5リードを備えた半導体部品を組み立
てた混成集積回路基板を示す平面図、第2図ないし第4
図は従来の混成集積回路装置の製造方法を説明するため
工程を示す断面図、第5図は従来の混成集積回路装置の
製造方法により組み立てられた場合の混成集積回路装置
の平面図、第6図はこの発明の混成集積回路の製造装置
の一実施列な説明するための断面図、第7図はこの発明
の混成集積回路装置の製造方法により組み立てた混成集
積装置の平面図である。 1・・・混成集積回路基板、2・・・導体、3・・・半
田ベースト、4・・・チップ部品、5・・・フラットリ
ードな有する半導体部品、6・・・フラットリード、8
・・・点滴容器、9・・・フラックス、3a・・・半田
。 なお1図中同一符号は同一または相当部分を示す。 代理人  葛 野 信 − 子1図
Figure 1 is a plan view showing a hybrid integrated circuit board assembled with semiconductor components equipped with 5 flat leads; Figures 2 to 4;
The figures are cross-sectional views showing steps for explaining a conventional method for manufacturing a hybrid integrated circuit device, FIG. 5 is a plan view of the hybrid integrated circuit device assembled by the conventional method for manufacturing a hybrid integrated circuit device, and FIG. The figure is a sectional view for explaining one embodiment of the hybrid integrated circuit manufacturing apparatus of the present invention, and FIG. 7 is a plan view of the hybrid integrated circuit device assembled by the hybrid integrated circuit device manufacturing method of the present invention. DESCRIPTION OF SYMBOLS 1... Hybrid integrated circuit board, 2... Conductor, 3... Solder base, 4... Chip component, 5... Semiconductor component with flat lead, 6... Flat lead, 8
...Drip container, 9...Flux, 3a...Solder. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Shin Kuzuno - Child 1

Claims (1)

【特許請求の範囲】[Claims] 混成集積回路基板上に半田ペーストを印刷し、この半田
ペーストの上にフェースボンディング用のフラットリー
ドを多数備えたモールドタイプの半導体部品を仮付けし
、この仮付は後に半田リフローする際に半導体部品のモ
ールド部に7ラツクスを滴下しながら半田付けを完了す
ることを特徴とする混成集積回路装置の製造方法。
A solder paste is printed on a hybrid integrated circuit board, and a mold type semiconductor component with many flat leads for face bonding is temporarily attached onto the solder paste. A method for manufacturing a hybrid integrated circuit device, characterized in that soldering is completed while dropping 7 lux onto a mold part.
JP56204652A 1981-12-16 1981-12-16 Method of producing hybrid integrated circuit device Pending JPS58105594A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56204652A JPS58105594A (en) 1981-12-16 1981-12-16 Method of producing hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56204652A JPS58105594A (en) 1981-12-16 1981-12-16 Method of producing hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS58105594A true JPS58105594A (en) 1983-06-23

Family

ID=16494031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56204652A Pending JPS58105594A (en) 1981-12-16 1981-12-16 Method of producing hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS58105594A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130196A (en) * 1983-12-16 1985-07-11 松下電器産業株式会社 Soldering method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130196A (en) * 1983-12-16 1985-07-11 松下電器産業株式会社 Soldering method

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