JPS58105478A - Buffer memory circuit - Google Patents

Abstract

PURPOSE:To shorten the clear time of a buffer memory, by using a pair of memory among plural effective bit memories for control of a buffer and using other bit memories to execute clearing actions in parallel. CONSTITUTION:The effective bit memories 22 and 23 are provided, and just a pair of bit memories is used for the control of a buffer. The parallel clearing actions are peformed with other bit memories. When a clear indication of the buffer memory is given, the memory bit with which the clearing action is over is switched among those to which the parallel clearing actions are given. In such a way, the clearing action is quickly finished for a buffer memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Description of the technical field to which the invention pertains] The present invention relates to a buffer memory circuit in a data processing device.

[Description of prior art]

In recent years, with the expansion of computer application technology, there has been a demand for ultra-high-speed computers that can perform numerical calculations at ultra-high speed. As a parallel processing system for realizing this ultra-high-speed computer, the one shown in FIG. 1 is known. FIG. 1 is a block diagram of main parts of a conventional parallel processing system. That is, a plurality of processor elements 1. ~1n
A parallel processor 1 consisting of a plurality of memory modules 2
A data memory 2 consisting of ~2n, a control processor 3,
It consists of a control processor memory 5 and a memory switch 6.

That is, the control processor 3#i and the parallel processor 1 are activated and synchronously controlled, and the 1 control processor 3#i accesses the setter memory 5 and the data memory 2.

The parallel processor l is a part that executes arithmetic operations of a user program under the control of the control processor 3, and when activated by the control processor 3, it automatically executes n processor elements l, ~1nell processor elements l, The instructions can be executed independently of ~ln. Data memory 2 includes parallel processor l and control processor 3
This is a memory that is commonly accessed from n and mainly stores data processed by parallel processor l. The memory switch 6 is a crossbar-type switch that controls data access requests between the parallel processor 1 and the data memory 2, and is used to connect any t processor elements 1, to 1n to any memory module 2.
~2n can be requested for access. Further, an access request from the control processor 3 to the data memory IJ 2 is also made via this memory switch 6. The control processor memory 5 is a memory for storing programs and data to be executed on the control processor 3, and is also used as an intermediate buffer for data stored on the data memory 2.

FIG. 2 shows the processor element l explained in FIG.
It is a principal part block block diagram about one of ~1n. Each processor element 1 is composed of a program memory 101 for the processor 1, a data memory 11 for the processor 101, and an arithmetic execution unit 12. That is, the processor program memory 10 is a program memory that stores a program to be executed given to the processor elements 1, .about.lnK from the control processor 3. The processor data memory 11 is a data buffer memory that stores part of the data stored in the data memory 2 to be processed by the reflow processor elements l, to 1n according to instructions from a program stored in the processor program memory IOK. It is. Arithmetic unit 12Fi Processor program memory IOK This unit performs arithmetic processing on the data in the data memory 2 according to instructions from the stored program, and stores the results in the data memory 2.

In the conventional parallel processing system configured in this way, in order to execute a certain group of arithmetic processing given from an external device, the control processor 3Fi first converts the program to be processed by each processor element l, to ln into a processor program. Each processor element 1.
The data required by ~1n are stored in the data memory 2 all at once. With this kind of thing, 11yll @ processor 3Fi
Processor element 1. .about.ln is activated and waits until execution completion reports are received from all processor elements 1.about.Ll.

(The intermediary processor elements 1. to 1n each independently perform arithmetic processing on the data given to the data memory 2 using the program given to the processor program IOK,
This result is stored in data memory 2. After the control processor 3 retrieves the calculation results from the data memory 2 based on the execution completion reports from all processor elements 11 to ln,
In order to execute the next group of arithmetic operations, programs and data are similarly stored in the program memory IO and data memory 2 for each processor, respectively.

In such a parallel processing system, it is necessary to clear all entries in the processor data memory 11t'1 as a buffer memory in the processor elements 11-ln each time the control processor 3 replaces data in the data memory 2. Conventionally, clearing the buffer memory is accomplished by clearing a set of valid bit memories that store valid bits indicating whether each entry in the buffer memory is valid or not, and this operation is controlled by microinstructions. There is. Therefore, during the buffer memory clearing operation, the processing device including the buffer memory is exclusively used for this operation. On the other hand, the standard capacity of the buffer memory in current large machines is 64 KB, and the number of entries is, for example, 1024.

Therefore, clearing such a buffer memory clears a valid bit memory of Fi1 bits x 1024 capacity, devoting the processing unit to the clearing operation for 1024 microinstruction steps.

However, in cases such as parallel processing systems, it is necessary to clear the buffer memory while the user program is running.
The long-term control processor 3 is connected to the processor element 1. ~1ni-111L, which has the disadvantage of significantly reducing system processing performance.

[Object of the present invention]

The present invention improves this point, and aims to provide a buffer memory device that can shorten the buffer memory clearing time and improve system performance.

[Summary of the invention]

The present invention provides n sets of valid bit memories each storing n valid bits indicating whether each entry of a buffer memory is valid or not, a clearing circuit for clearing each valid bit memory independently of a signal group, and A connection circuit that connects one set of bit memories to the buffer memory partition circuit and the other n-1 sets to the clear circuit, and n-1 sets of valid bits connected to the clear circuit Kwr by a clear instruction to the buffer memory. Check whether each memory has been cleared, and if not all have been completed, use of the buffer memory is made to wait until completion of one or more sets is detected, and if completion of - or more sets is detected. A control circuit connects a set of valid bit memories that have been cleared to the buffer memory control circuit Kl, and switches the 1# connection circuit so that the valid bit memory connected to the buffer memory control circuit is connected to the clear circuit. It is characterized by having the following.

[Example of the present invention]

An embodiment of the present invention will be described based on the drawings.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention. FIG. 5 shows only the effective bit memory control circuit, which is a feature of the present invention, and other circuits of the buffer memory circuit are omitted from this diagram. In this example, there are two sets of valid bit memories.

The circuit shown in FIG. 3 operates in synchronization with a clock supplied to control the buffer memory function, and includes a flip-flop 15 that holds a clear instruction signal 101 for the buffer memory circuit, and a 10-bit clear address. a counter 16 that outputs the signal 102;
CARRY signal 1 of the carry output from the most significant bit of
A flip-flop 17 for holding 03 is provided. The output of the HCLEAR signal 104 and the inverted output 105 of the flip-flop 15 is connected to the input terminal of an AND circuit 18 which outputs the logical product of the output, the W/T signal 106. It's dark. In addition, the HOLICAR signal 104 and the flip-flop 17
The READY signal 107, which is the output of the above, is respectively led to the input terminal of an AND circuit 19 which outputs the CHANGE signal 108, which is the logical product thereof. This CH NGR signal 108 is connected to a delay circuit that delays the main signal by one clock and outputs an RK31CT signal 109 for resetting the counter 16, flip-flop 15, and flip-flop 17.
Every time 08 becomes logic "1", output 8 hill LKOT signal 1
They are each led to a flip-flop 21 which inverts 10. Further, an effective bit memory n and an effective bit memory field having a capacity of 1024×1 bits are provided.

Also, when the 8PL OT signal 110 is logic "0", a valid bit memory IJ is supplied as a buffer memory-like function.
WRIIIj signal 121 instructing write permission of 22;
VAL as data to be written to the valid bit memory 22
outputs a signal 122 and a 10-bit memory DDRB8B signal 123 that supplies the address of the valid bit memory n, and a logic "1" signal 124 that always allows writing of the valid pit memo IJ 22 when the 8KLIOT signal 110 is logic "1". , the logic “0” of the data written to the valid bit memory n
” signal 125 and a 10-bit clear address signal 1 that supplies the address to be cleared to the valid bit memory 4.
A selection circuit 24 that outputs 02 and an 81LKOT signal 11
When 0 is logic "0", a logic "1" signal 124 that always allows writing of the valid pit memo 1323, a logic rOJ signal 125 of write data for each valid bit memory, and an address to be cleared of the valid bit memory phantom are supplied. Clear address signal M 102 t-output 1.81c When the IdccT signal 110 is logic "1", valid bit memo IJ 23
The WRIIC signal 121 instructs write permission of the valid bit memory, the signal 122 from VAL as the write data of the valid bit memory, and the ADDRKS as the address of the valid bit memory.
A selection circuit 5 that outputs a B signal 123 is provided. Furthermore, the 5RLIeOT signal 110 is 1mfi1. r
When OJ, the output of effective bit memory n is 5ICLKOT.
The selection circuit 26 outputs the output of the valid focus memory as a V signal 127 when the signal 11G is logic "1".

FIG. 4 is a time chart explaining the operation of FIG. 3. The CLOCK signal in 41jA is a clock equivalent to the control clock for the buffer memory function.

The characteristic operation of the present invention will be explained using such a circuit configuration. At the time of signal 00 at 0L00, 131! iLl.

T41! Since signal 110 is logic "0" K, effective bit memory 22KFiWRI'rl signal 121. VAL
The ID signal valid bit memory 23 has a logic “1” signal 12.
4, logic “0” signal 125 and clear address signal 1
02 is supplied, and the output of the valid bit memory n is selected as the V signal 127 indicating whether or not the buffer memory entry at the address of the ADDRK8E1 signal 123 is valid.

That is, the effective bit memory 22Fi is used for buffer memory control, and the effective bit memory field is in the process of being cleared.

If a carry occurs in the counter 16 with the 0LOOK signal 1, the CARRY signal 103 becomes logic "1", the flip-flop 17 is set, and the RItADY signal 10
7 becomes logical "1". This means that all 1024 bits of the valid bit memory n are written with "0" by the clear address signal 102 counted by the counter 16, and the clearing is completed. 0LOOK
Signal 3 indicates CIFj to clear the buffer memory.
When the AR signal 101 becomes logic "1", the flip-flop is set, the HOLm R signal 104 becomes logic "1", and the HANGI signal 108 becomes logic "1". When the 0HANG abuse signal 10g becomes logic "IJK", the flip-flop 21 is inverted and the smL11COT signal 11
0 becomes logical "1". EIICLBO'r signal 110
When K'& is a logic "1", the selection circuit word, selection circuit 24 and selection circuit 26 are switched, the effective bit memory phantom is used for buffer memory control, and the effective bit memory n is enabled for clearing operation. chocK Confucian No. 4 Te RIE II
? When the signal 109 becomes logic "1" K, flip 70 knob 1
5, counter 16 and flip-flop 17 are reset, HOLIAR signal 104, RKAI)Y signal 10
7 and cm NGK signal 108 become logic "0".

After CLOOK signal 5, the counter 16 counts from 0 and the valid bit memory 22 is cleared bit by bit.

By instructing the buffer memory to clear with the CLOOK signal 1026 (3Idem R signal 101 becomes logic “1”)
If this occurs, since the clearing operation of the valid bit memory n has not yet been completed, the WA-TE signal 106 for making the use of the buffer memory wait until the clearing operation is completed becomes logic "1". 0LOOK signal 1028 and power 9 input 16 is cbo
This means that it has been counted 1024 times since ax signal 5.C
The ARRY signal 103 becomes logic "1" and the flip-flop 17 is set. - Since the R1 module DY signal 107 becomes logic "1", the 0RANGEffi signal ios becomes logic "1", and the W module T signal 106 becomes logic "0", CH
The 81LIOT signal 11G is inverted by the AMG signal 108K and becomes logic "0". This enables the valid bit memory n to be used for buffer memory control, and enables the valid bit memory field to be cleared. CLOOK signal 1
At 029, the RIB11f signal 109 becomes logic "1" and the flip-flop 15, counter 16 and flip-flop 17 are reset, so HCI,]! fAR signal 108 and R1C DY (@No. 107 is logic “0”
becomes. C'LOCK signal 1030 to R hill 8? signal 1
09 becomes logic "0".

In this way, the memory has multiple valid bits, only one set is used for buffer memory control, and the others are cleared in parallel, and when a buffer memory clear instruction is given, the valid memory bits are cleared in parallel. Since it is used by switching between the buffer memory and the one that has been cleared, the buffer memory can be cleared in a shorter time.

[Detailed description of the invention]

As described above, according to the present invention, it is possible to shorten the buffer memory clearing time and improve system performance.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of a conventional parallel processing system. Figure 2 shows one of the processor elements shown in Figure 1! Part block configuration diagram. FIG. 3 is a block diagram of an inspector according to an embodiment of the present invention. FIG. 4 is an operation time chart of the above embodiment. l...Parallel processor, 11-ln...Processor element, 2...Data memory, 2. ~2n...
Memory module, 3... Control processor, 5...
Control processor memory, 6...Memory switch, 10
. . . Program memory for processor, 11 . . Data memory for syrocessor, 12 . . Arithmetic unit, 15
．． 17.21...Flip-flop, 16...Counter, 22, 23...Valid bit memory, 24-26
...Selection circuit. Patent Applicant NEC Corporation Agent and Patent Attorney Sansuke Izunao 1 Figure j'i'52E21 Ivy Figures 3 and 2

Claims (1)

[Claims] (1) In a buffer memory circuit that stores a copy of information in the main memory, there are n valid bit memories each storing a valid bit indicating whether each entry in the buffer memory is valid; A clearing circuit that clears each bit memory independently of the other bit memories, and connecting means that connects one set of the valid bit memories to a control circuit of the buffer memory and connects the other (n-1) sets to the clear circuit. , n - 1 sets of the above valid bits connected to the clear circuit by a clear instruction to the buffer memory.
It is checked whether the clearing of the buffer memory has been completed, and if all of them are not completed, the use of the buffer memory is made to wait until the completion of clearing of one or more sets of the above valid bit memories is detected, and one set of the above valid bit memories is cleared. When the above-mentioned completion of clearing is detected, one set of the valid bit memories that have been cleared is transferred to the set of the valid bit memories (sofa memory control circuit Km), and the valid bit memories that were connected to the buffer memory control circuit Km are transferred to the clear circuit. A buffer memory circuit characterized in that the above-mentioned connection means is controlled so as to be connected to the buffer memory circuit.