JPS58104516A - Analog delay line - Google Patents

Abstract

PURPOSE:To form a multistage delay line and a tapped multistage delay line, by connecting an arbitrary number of delay lines consisting of a switched capacitor (SC) circuit and an integration circuit in cascade. CONSTITUTION:An SC circuit 30 consisting of a switch and a capacitor stores analog signals temporarily. Switches 32-35 consist of MOSFETs. An integration circuit 50 comprising an operational amplifier 51, a capacitor 52 and a switch 53 outputs a signal when a signal charge of a capacitor 31 is transferred to the capacitor 52. In applying a pulse phi1 to a terminal 41, the capacitor 31 is charged, and when the pulse phi1 is disappeared, the charge is stored. Since a pulse phi2 is set on or off to a terminal 57, the integration circuit 50 is reset and the potential at a terminal 56 is zeroed. In setting a pulse phi3 to a terminal 42, a signal charge in the capacitor 31 is transferred to the capacitor 52 and an output delayed than an input signal by one period appears at the terminal 56. Signals inputted at each period are outputted with delay by one period each.

Description

[Detailed description of the invention] The present invention relates to effective table delay for analog signal processing.

In recent years, central office equipment and terminal equipment for telephone lines and digital communication lines have become faster, lower power consumption, and smaller.

There has been a strong demand for low prices. Rounding that satisfies this requirement requires analog signal processing or device integration. One of the devices for which integration is currently strongly required is an auto-equalizer for removing distortion of digital signals caused by code amount interference. To date, no integration of automatic equalizers has been achieved. The reason for this is
It is ideal for these applications as a delay line for analog signals, which is an important component of filters including automatic equalizers.

This is also because an analog signal delay line that can be integrated has not been realized.

FIG. 1 is a block diagram for explaining a conventional delay #. ] is an input terminal to which an analog input signal is supplied, 2 is an output terminal from which an analog delayed signal is obtained, 11, 12.1
3 is a delay stage which delays No. 171 by a fixed time T, respectively. Therefore, if #N delay stages are connected in cascade as shown in FIG. 1, the human input signal f supplied to the terminal l can be obtained at the terminal 2 after NT between fti. t4
FIG. 2 is a plotter diagram of a conventional tapped slow # line, which is the basic component of an acyclic filter. 1OF
i Analog signal input terminals 11, 12.13 are the same delay elements as the same numbered elements in FIG.
It is a rounded tap terminal that receives the delayed signals from the delay stages 11, 12, and 13. Therefore, by cascading N delay stages and providing a tap terminal at the output of each delay stage, it is possible to obtain N delayed signals that differ by T each hour.

Conventionally, as a means to realize such a delay line or tapped delay m'fr, delay stages 11, 12, and 13 are each LR.
A passive circuit composed of passive elements such as C was used. But this method.

Each j! cannot obtain a sufficiently long delay time! In addition, there are many problems such as the inability to accurately equalize the delay times of 1tR, and the number of manufacturing steps required.

A significant drawback was that it was impossible to integrate on a single semiconductor chip.

Analog delay line and tagged analog delay 11! Other conventional means of constructing ILs include the well-known nine charge-coupled devices (CCDs) and the top-gated devices (B
There is a method using a charge transfer device (e'rD) such as BL). However, these devices also suffer from rounding traps, which are listed below and are major obstacles to realizing compact, low-power analog integrated circuits.

1) Since the CTD is essentially a semiconductor device with an rfiMO8 structure, it is possible to integrate it with an NMOS device. However, the cM of the integrated circuit mounted on CTD 1
osMo conversion is technically very difficult, and it is almost impossible to realize it considering the number of man-hours and yield.
CTD t-There is a problem in that the power consumption of an on-chip integrated circuit is large.

2) 5V single-lE# or ±5■ dual power supply, etc.

In addition to these power supplies, the CTDij requires a power supply of IOV or higher for the chest circuit that is produced at low voltage. For this reason, it is almost hopeless to put a CTD-equipped circuit into practical use for a nine-terminal device.

3) Although a high voltage is required as mentioned in the second product, the dynamic range is extremely small and it is not possible to process large amplitude input signals.

4) Since the reference level of the input signal that is normally supplied is the ground level, when applying this to the CTD, it is necessary to superimpose a DC bias. The dead output signal is also superimposed on the iI DC IA component and output. C
TD input stage.

The output stage tap circuit requires a level shifter to convert input/output signals into a DC level tube, making the circuit configuration complicated.

The problems with eTD slow grinding wires have been described above. However, with the integration of analog signal processing circuits such as automatic equalizers, no rounding integrated automatic equalizer has been realized so far, except for UTD iH, which does not have an analog delay line that can be integrated.

The purpose of the present invention is to solve the problems of the above-mentioned passive delay line (CTL) delay line, and to provide an efficient form of low power consumption.

An object of the present invention is to provide an analog delay line suitable for analog integrated circuits.

According to the present invention, a switched capacitor circuit including at least a switch and a capacitor;
and an integrating circuit including a capacitor and an operational amplifier,
An analog delay line is obtained, which is characterized in that the output terminal of the switched capacitor circuit and the input terminal of the integrating circuit are connected to each other.

Further, according to the present invention, there is provided a switched capacitor circuit including at least a switch and a capacitor, and an integrating circuit including at least a switch, a capacitor, and an operational amplifier, and the output terminal of the switched capacitor circuit and the input terminal of the integrating circuit are provided. By cascade-connecting a plurality of analog delay lines each having terminals connected to each other, an analog delay line with 41 degrees can be obtained.

Further according to the invention, a switched capacitor circuit includes at least a switch and a capacitor.

an integrating circuit including at least a switch, a capacitor, and an operational amplifier, a plurality of stages of analog delays Im each connected in cascade by connecting an output terminal of the switched capacitor circuit and an input terminal of the integrating circuit; An analog delay line characterized in that a tap output terminal is provided at the output terminal of each stage is obtained.

By using the analog delay line according to the present invention,
Accurate delay time can be obtained. Since it does not require a high power supply voltage like a CTD and can be integrated with 0MO8, it is possible to reduce the power consumption of the integrated circuit. Dynamic range is expanded. Since a level shifter is not required, the circuit configuration is simple.

Many advantages can be obtained, such as:

The present invention will be explained below with reference to the drawings.

Figure g3 is an example of the analog signal extension 1 of the present invention.

Delays the analog input signal by one period of the drive pulse,
This is the output delay line. This circuit Fi also corresponds to each delay stage 11.12.degree. 13 shown in FIGS. 1 and 2. 3
0 is a switched capacitor (8W1tched Capa-citor, S
A circuit (abbreviated as C) that temporarily stores analog signals. 31 is a capacitor with a capacitance CI. 32,3
3.34.35 is Sui.

Here, as an example, an MO8 field effect transistor (referred to as MOSFET) is used. 36,
37, 38, 39, 40, 41, and 42 are terminals. 5
0 is the operational amplifier 51. Capacitor 52 with capacitance C2.
An integrating circuit consisting of a switch (here shown as a MOSFET) 53 and terminals 54, 55, 56, 57, which outputs a signal when a good signal charge accumulated in the capacitor 31 is transferred to the capacitor 52. .

Fig. 4 shows the ninth cross, Qbals φl, φ2. This is an example of a timing diagram showing the potentials of φ3 and terminal 36.38°56.

Reference numeral 60 denotes a pulse φl supplied to the terminal 41, and when this pulse is at the high level and low level, the switches 32 and 33 become conductive and non-conductive, respectively (that is, when the pulse 60 is turned on, the switch 32 ,!: 33 is turned on and capacitor 31 is charged.

When pulse 60 turns off, switches 32 and 33 turn off). Similarly, 70 is the pulse φ supplied to the terminal 57.
2, when this turns on, the switch 53 turns on and resets the integrating circuit 50 (ie.

discharge the charge accumulated in the capacitor 52).

When the pulse -3 is supplied to the 80rfi terminal 42, switches 34 and 35 are turned on when the pulse is turned on.

The charge accumulated in the capacitor 31 is transferred to the capacitor 52.
When the pulse 80 is turned off, the switches 34 and 3
5 is off. 90 is an analog input signal supplied to the terminal 36, 100 is the potential of the terminal 38, and 110 is an output signal obtained from the terminal 56. Note that 90 is shown by a broken line, overlapping with 100.

Next, using Fig. 3 and Fig. 4, explain how the human power signal at the terminal 360 is output to the terminal 56 with a delay of one cycle period T of the drive pulse. It can show the shaving period T. When the pulse 60 is turned off during the current phase 61, the capacitor 31 is charged until the terminal 38 is at the same level as the input signal. Next, when the pulse 60 is turned off, the capacitor 31Fi is turned off and a charge corresponding to the product of the input signal level Vl at the time of death and the capacitance C1 of the capacitor 31 is held. This state is indicated by 100.

It is then held until pulse 80 is turned on. On the other hand, the period during which the input signal is stored in the capacitor 31 (pulse 6
Since the pulse 70 turns on and off during the period from when the pulse 0 turns off until the pulse 80 turns on, the integrating circuit 50 is reset and the potential at the terminal 56 returns to zero volts.

After reset, when the pulse 80 is turned on, the signal charge (VIXCI) stored in the capacitor 31 is transferred to the capacitor 52, and an output delayed by one cycle from the input signal appears at the terminal 56, as shown at 110. Since the magnitude of the output gii is given by Fi(eixVl)/C2, C
When I and C2 are exactly equal.

The amplitude of the output signal is the amplitude v of the input signal as shown at 110.
It becomes equal to l. Note that in the connection method shown in Figure i@3, the code of the output information is the same as that of the input signal, that is.

It is normal rotation. On the other hand, terminals 40 and 55'Ift, terminal 39
and 54t, respectively i! If it is connected, the polarity will be reversed and nine outputs will be obtained. The input signal v2 sampled in the next cycle AQ62 is also output after one cycle of the drive pulse, as described above.

Although it has been shown above that the signals sampled in the two periods 61 and 62 are output with a delay of one period T, the signals input in each subsequent period are also output with a delay of one period.

By cascading a plurality of delay lines each consisting of the SC-path 30 and the integrating circuit 50 shown in FIG.

A multi-stage analog signal delay line is realized. This is JI5
As shown in the figure. 211, 212, 213t; t each third
9. It is the same circuit as the delay line shown in the figure, and each delay 42ij is connected by a common line 41231, 232, 233, respectively. The driving pulses φl, φ2. φ3 is supplied respectively. Therefore, the delay −211°212.2131k
If N pieces are connected in cascade, a delayed signal delayed by N times the period of the dynamic pulse can be obtained from the final stage delay line 213. If tag terminals 221, 222, and 223 are provided from the output terminals 56 of each delay -211, 212, and 213, respectively,
A tapped analog signal delay line is configured.

Note that since the operation of the single delay line is exactly the same as that of the delay line shown in FIG. 3, the explanation thereof will be omitted here. Also delayed @21
2. The circuit configuration of 213 is exactly the same as the delay line 211 or the delay line in FIG.

i#m is omitted.

The analog signal delay a41 according to the present invention has been explained above.

This delay consists of an SC1 path and an integrating circuit.

By cascading an arbitrary number of delay lines, a multi-stage j! ! #, - and tapped multi-stage delays - can be implemented. According to the delay of the present invention.

It can fire a number of W values listed below.

1) Accurate and extremely slow a time can be obtained, which is impossible with passive slow speed.

2) Since the delay m- of the present invention is composed of an SC circuit and an integrating circuit, it is possible to use a cMos structure, which is impossible with a CTD. Therefore, it is possible to make the entire analog signal processing integrated circuit including one peripheral circuit CMOa, and it is also possible to achieve a reduction in power consumption that is suitable for practical use. .

3) It does not require high power supply voltage like CTD.

It is particularly advantageous when applied to terminal devices of digital transmission systems.

4) Unlike CTD, the S/N is large because the dynamic range of the operational amplifier can be used effectively.

An integrated circuit with a wide dynamic range is realized.

5) Unlike CTI), there is no need to convert the DC level of input/output signals, so the single circuit configuration can be simplified.

Note processing is easy.

6) Unlike CTD, there is no need for an arbitrary tap Uwr, and the output terminal of each delay line connected in cascade can be used for tap output.

The above describes the present invention with an example of a specific circuit configuration and a driving method, and describes how the present invention can be imitated. Book delay II! Needless to say, the present invention is widely applied to signal processing circuits such as one-cycle filters and acyclic filters, as well as slow abrasion of audio and video signals.

In addition, in explaining the present invention, the JSC circuit and the integrating circuit have been explained using the circuit configurations 30 and 50 in Fig. 3, respectively, but if the desired function is achieved, these circuit configurations or connection methods It is not limited. Also 94
The timing and signal waveform of the noise shown in the figure are also examples, and the present invention is not limited thereto. Switches 32 and 33 in Figure 3
．． 34,35゜53 is ζ where d- MOSFET as an example
I used =i.

Any switch, including CMU8) transistors, may be used as long as the switch function is satisfied.

[Brief explanation of the drawing]

FIG. 1 is a ninth block diagram explaining a conventional analog delay fs, FIG. 2 is a block diagram of a conventional tapped analog delay line, and FIG. 3 is a configuration diagram of an analog signal delay line of the present invention. , FIG. 4 shows the timing of the drive pulse and waveforms of the input/output signals for driving the delay lN shown in FIG. 3, and FIG. , multiple analog signal delay lines. In FIGS. 1 and 2, 11j12.13 is a delay stage. Completed 3 diagrams. In FIG. 5, 30 is an SC circuit, and 50 is an integrating circuit. 31.52 is a capacitor, 32.33, 34, 35°5
3 FiMO8FET switch, 51Fi operational amplifier. 211, 212, and 213 are one delay stage of analog delay lines consisting of 30 and 50, respectively, 221, 222°2
23 is a tap terminal, and 231, 232, and 233 are common wiring lines to which driving pulses are applied.

Claims (1)

[Claims] 1. A switched capacitor circuit including at least a switch and a capacitor, and at least a switch. and an integrating circuit including a capacitor and an operational amplifier,
An analog delay circuit whose output terminal of the switched capacitor circuit and the input terminal of the integration circuit are connected to each other and whose value is 1-value. 2. A switched capacitor circuit including at least a switch and a capacitor; and at least a switch. and an integrating circuit including a capacitor and an operational amplifier,
9. An analog delay line characterized in that a plurality of stages of analog delay lines are connected in cascade, each having an output terminal of the switched capacitor circuit and an input terminal of the integration circuit connected to each other. 3. A switched capacitor circuit including at least a switch and a capacitor; and at least a switch. and an integrating circuit including a capacitor and an operational amplifier,
A plurality of stages of analog delays m formed by connecting the output terminal of the switched capacitor circuit and the input terminal of the integrating circuit are connected in cascade, and a tap output terminal is provided at the output terminal of each stage. Analog slow am.