JPS58103068A - ベクトル・デ−タ乗算処理方式 - Google Patents

ベクトル・デ−タ乗算処理方式

Info

Publication number
JPS58103068A
JPS58103068A JP56201968A JP20196881A JPS58103068A JP S58103068 A JPS58103068 A JP S58103068A JP 56201968 A JP56201968 A JP 56201968A JP 20196881 A JP20196881 A JP 20196881A JP S58103068 A JPS58103068 A JP S58103068A
Authority
JP
Japan
Prior art keywords
data
multiplication
circuit
vector data
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56201968A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6136678B2 (enExample
Inventor
Takanao Kamei
亀井　孝尚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56201968A priority Critical patent/JPS58103068A/ja
Publication of JPS58103068A publication Critical patent/JPS58103068A/ja
Publication of JPS6136678B2 publication Critical patent/JPS6136678B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8053—Vector processors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)
  • Character Discrimination (AREA)
  • Image Analysis (AREA)
JP56201968A 1981-12-15 1981-12-15 ベクトル・デ−タ乗算処理方式 Granted JPS58103068A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56201968A JPS58103068A (ja) 1981-12-15 1981-12-15 ベクトル・デ−タ乗算処理方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56201968A JPS58103068A (ja) 1981-12-15 1981-12-15 ベクトル・デ−タ乗算処理方式

Publications (2)

Publication Number Publication Date
JPS58103068A true JPS58103068A (ja) 1983-06-18
JPS6136678B2 JPS6136678B2 (enExample) 1986-08-19

Family

ID=16449744

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56201968A Granted JPS58103068A (ja) 1981-12-15 1981-12-15 ベクトル・デ−タ乗算処理方式

Country Status (1)

Country Link
JP (1) JPS58103068A (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0664694U (ja) * 1993-02-24 1994-09-13 株式会社共栄商会 パチンコ機用球受装置

Also Published As

Publication number Publication date
JPS6136678B2 (enExample) 1986-08-19

Similar Documents

Publication Publication Date Title
EP0890899A2 (en) Multiplication method and apparatus
JPH02504339A (ja) ガロア体における乗算器‐加算器及びディジタル信号処理プロセッサにおけるその使用
KR960704266A (ko) 고속 이진 승산기용 개량된 웰레스-트리 가산기, 구조 및 방법
US5323338A (en) Pseudo-random sequence generators
US7103620B2 (en) Method and apparatus for verification of digital arithmetic circuits by means of an equivalence comparison
CN120281454A (zh) 用于算术电路的串行化的计算机实现的系统和方法
CN112491543A (zh) 基于改进的蒙哥马利模幂电路的ic卡解密方法
Qiu et al. Arithmetic and logic operations for DNA computers
JPS58103068A (ja) ベクトル・デ−タ乗算処理方式
CN114881239A (zh) 量子生成器的构造方法、装置、介质及电子装置
Rahman et al. An extensive karnaugh mapping tool for boolean expression simplification
US4325056A (en) BCD To binary converter
Homma et al. Evolutionary graph generation system with symbolic verification for arithmetic circuit design
CN116388954A (zh) 通用密态数据安全计算方法
Maurer Scheduling blocks of hierarchical compiled simulation of combinational circuits
KR20030009682A (ko) 가산기 기반 분산 연산의 가산 공유 정보 추출을 위한신경망 알고리즘 구현 방법
JP2682142B2 (ja) 乗算装置
CN114881238A (zh) 量子鉴别器的构造方法、装置、介质及电子装置
Tokuhara et al. Acquisition of characteristic block preserving outerplanar graph patterns by genetic programming using label information
CN116933879A (zh) 一种量子态的确定方法及装置
SU1157542A1 (ru) Устройство дл умножени
CN113517983B (zh) 生成安全计算密钥、进行安全计算的方法及装置
JP3921259B2 (ja) 記号的処理を可能にする非記号処理装置と、情報処理システム及びその自動コーダ
SU656059A1 (ru) Арифметическое устройство
Kala et al. A 32-bit binary floating point neuro-chip