JPS58101519U - input selection circuit - Google Patents
input selection circuitInfo
- Publication number
- JPS58101519U JPS58101519U JP19690281U JP19690281U JPS58101519U JP S58101519 U JPS58101519 U JP S58101519U JP 19690281 U JP19690281 U JP 19690281U JP 19690281 U JP19690281 U JP 19690281U JP S58101519 U JPS58101519 U JP S58101519U
- Authority
- JP
- Japan
- Prior art keywords
- input selection
- selection circuit
- analog switch
- muting
- selection signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
図面はいずれも本考案実施例に係り、第１図は回路ブロ
ック図、第２図は第１図の部分回路図、第３図は動作説
明の為の要部波形図、第４図は入力選択指示手段の回路
図である。
主な図番の説明、１． ２． ３・・・・・・アナログ
スイッチ、８・・・・・・入力選択支持手段、１２，１
３゜１４・・・・・・遅延手段、４・・・・・・ミュー
ト手段、１５・・・・・・ミュー、ト制御手段。The drawings are all related to the embodiment of the present invention, and Fig. 1 is a circuit block diagram, Fig. 2 is a partial circuit diagram of Fig. 1, Fig. 3 is a main part waveform diagram for explaining the operation, and Fig. 4 is an input diagram. FIG. 3 is a circuit diagram of selection instruction means. Explanation of main figure numbers, 1. 2. 3... Analog switch, 8... Input selection support means, 12, 1
3゜14...Delay means, 4...Mute means, 15...Mute control means.
Claims (1)
該アナログスイッチの選択信号を出力する入力選択指示
手段と、該アナログスイッチに印加される該選択信号を
遅延する遅延手段と、上記アナログスイッチの出力をミ
ュートするミュート手段と、該選択信号により上記ミュ
ート手段を一定期間能動とするミュート制御手段とを備
える入力選択回路。Multiple analog switches each corresponding to multiple inputs,
input selection instructing means for outputting a selection signal of the analog switch; delay means for delaying the selection signal applied to the analog switch; muting means for muting the output of the analog switch; and mute control means for activating the means for a predetermined period of time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19690281U JPS58101519U (en) | 1981-12-28 | 1981-12-28 | input selection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19690281U JPS58101519U (en) | 1981-12-28 | 1981-12-28 | input selection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58101519U true JPS58101519U (en) | 1983-07-11 |
Family
ID=30110129
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19690281U Pending JPS58101519U (en) | 1981-12-28 | 1981-12-28 | input selection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101519U (en) |
-
1981
- 1981-12-28 JP JP19690281U patent/JPS58101519U/en active Pending
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