JPS58101399U

JPS58101399U - sample hold circuit

Info

Publication number: JPS58101399U
Application number: JP19722481U
Authority: JP
Inventors: 紀之山下
Original assignee: ソニー株式会社
Priority date: 1981-12-29
Filing date: 1981-12-29
Publication date: 1983-07-09

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は従来のサンプルホールド回路を示すブロック図
、第２図は本考案に依るサンプルホールド回路を示す接
続図である。１・・・・・・サンプルホールド回路、２・・・・・・
入力可変直流電圧信号源、４・・・・・・外部端子、５
・・・・・・バッファ回路、１４・・・・・・バイアス
回路、１９・・・・・・ドライブ回路。FIG. 1 is a block diagram showing a conventional sample and hold circuit, and FIG. 2 is a connection diagram showing a sample and hold circuit according to the present invention. 1...Sample hold circuit, 2...
Input variable DC voltage signal source, 4...External terminal, 5
... Buffer circuit, 14 ... Bias circuit, 19 ... Drive circuit.

Claims

[Claims for Utility Model Registration] 1. In a sample-and-hold circuit configured to sample an input terminal using a sampling pulse, charge and discharge a capacitor, and output the terminal voltage of the capacitor as a sample-and-hold voltage, when the sampling pulse is applied a voltage comparison circuit that compares the input voltage with the terminal voltage of the capacitor each time the input voltage is input, and receives the output of the voltage comparison circuit and generates first and second bias voltages having different bias levels according to the comparison results. A bias circuit, a charging transistor and a discharging transistor that are turned on and off according to the first and second bias voltage numbers, and the capacitor is charged or discharged by the charging transistor or the discharging transistor. A sample hold circuit characterized by: 2. The voltage comparison circuit includes a transistor pair having an emitter-follower differential amplifier circuit configuration for comparing the input voltage and the sample-and-hold voltage, and a first current source connected to the transistor pair and on/off controlled by the sampling pulse. , and a second current source formed of a current mirror that receives the differential output obtained from the transistor pair as a comparison output and converts it into a corresponding current value, and the bias circuit is activated when the sampling pulse is not generated. A predetermined DC bias voltage between a power supply and ground is generated, and when the sampling pulse is generated, the bias voltage is changed and controlled by a current from the second current source, and the bias voltage of the bias circuit is controlled to change. A charging transistor and a discharging transistor of the emitter follower are connected in series between the power supply and ground through an overcurrent protection resistor, respectively, and the charging transistor and the discharging transistor are connected in series between the power supply and the ground, respectively, and the emitter follower is turned on and off according to the comparison result of the transistor pair. The sample according to claim 1 of the utility model registration claim, comprising a drive circuit consisting of a push-pull circuit that applies a charging current to the capacitor through the capacitor or flows a discharge current from the capacitor through the discharging transistor. hold circuit.