JPS58100755A - Signal display device - Google Patents

Abstract

PURPOSE:To recognize the presence of a fine pulse in a long observation time by making the sampling period of an input signal shorter than the writing period of a memory and then holding sampled information until it is written in the memory. CONSTITUTION:Only signals which are higher than a specified threshold level 35 among input signals 20-1-20-n are allowed to pass through an input gate 1, and a sampling circuit 2 extracts outputs 21-1-21-n at a shorter period than the writing period of a memory and holds them. Those held pieces of information are written in the memory 3 at the timing of a write clock 32 and while the holding by the sampling circuit 2 is released by a reset signal 31, address information 24 is updated by an address count signal 33. Said operation is repeated with regard to all areas of the memory 3 and the time relation among input signals is stored in the memory 3. After the writing to the memory 3 is completed, stored information is read out of the memory 3 and then displayed on a display part 4.

Description

DETAILED DESCRIPTION OF THE INVENTION Related to a signal display device that stores the stored information in the form of a signal, and then reads out the stored information and displays it on a cathode ray tube, etc. Conventionally, this type of signal display device has been used to store time relationships of input signals. The device is configured to designate a sample clock and write the sampled information into the memory while sequentially sampling input signals in accordance with the sample clock cycle.

After the writing to the memory is completed, the stored information is read out from the memory and displayed on a cathode ray tube or the like to display the time relationship of the input signals.

Therefore, the memory capacity for one input signal channel is N
If the bit and designated clock period are t seconds, the maximum observable time of the input signal is tN seconds. Therefore, in order to increase the maximum observable time, it is necessary to specify a long quadrupling period t. However, if t is made longer, the resolution becomes coarser because pulse widths shorter than t cannot be observed.

On the other hand, observers often want to capture the arrival of input signals with short pulse widths during a long observation period and recognize the approximate relative temporal relationship.

Conventional O signal display devices have not been able to meet such demands and have been extremely inconvenient.

An object of the present invention is to solve the above-mentioned drawbacks by making the sampling period of the input signal shorter than the writing period to the memory and retaining the sample information until writing to the memory. The existence of minute pulses in time is S!
An object of the present invention is to provide a signal display device that can be easily recognized.

In order to achieve the above object, the signal display device according to the present invention includes means for extracting and holding the input signal at a cycle shorter than the cycle at which the input signal is written into the memory, and releasing the holding of the cough input signal after writing the input signal to the memory. is provided so that an input signal having a pulse shorter than the memory write cycle can be displayed as having the same time width as the memory write cycle.

According to the above structure, the object of the present invention can be completely achieved.

The present invention will be described in more detail below with reference to the drawings and the like.

FIG. 1 is a block diagram mainly showing input signals and memory write control in an embodiment of the present invention. Input gate 1 receives input signals 20-1, 20-2,...
-Receive 20-n. The sampling circuit 2 extracts and holds the outputs 21-1, 21-2, ---21-n of the input gate 1 using a sample clock 30. Memory 3 is output 22-1.22-2 of sy-pull circuit 2, ----
Write rq-n sequentially input signal 20-1.20-2, -
Stored as time-related information of addition-n ◇ The display unit 4 displays information read from the memory 3.
The control unit 5 performs overall control such as designation of the write frequency for the printer 3, designation of a trigger, and display control.

The sampling clock generation circuit 6 generates a sample clock (
generate capital). A memory clock generation circuit 7 generates a control clock related to the memory 3.

The address counter 8 also generates address information 24 for the memory 3.

A signal 31 from the memory clock generation circuit 7 is a reset signal for releasing the hold of the sample circuit 2 after writing to the memory 3, a signal 32 is a write clock pulse for the memory 3, and a signal 33 is a pulse for instructing the address counter 80 to move. , signal 34 is a read timing signal of the memory read information device. The signal 35 from the control unit 5 is a signal specifying the threshold level of the input signal, and the signal 36
is an initial setting signal 1 for the address counter 8, a signal J is a display control signal for the display section 4, and a signal 1 is a signal specifying a cycle T for storing input signals.

An example of the time relationship between signals is shown in FIG.

As shown in FIG. 2, the cycle τ of the sample clock J is also made shorter than the memory write cycle T.

The shorter the sampling period τ is compared to the writing period T, the higher the input signal capture rate becomes.

Next, the operation of the signal display device described above will be explained with reference to FIG. 1 and FIG. 2.

First, the input signal extraction operation will be explained.

〇 Input signal 2Q-1.2 Initializes the address counter 8 using the address set signal at the start of operation.
G-2, -...-20-n is the threshold number designation 3
Only those higher than 5 will pass through input gate 1. The output of the input gate 21-1.21-2,...-1.
Extract with the 2nd sample clock 30 and hold until the reset signal comes. The role line of the sample black ivy garden is to remove short duration pulses as noise. This retained information 22-IS22-2,・
...-=22-n is written to the memory 3 at the timing of the write clock 32. Kops reset signal 31
At the same time, the address count signal and the address information U are updated.
Thereafter, the above operation is repeated for all areas of the memory, and the time relationships of the input signals 20-1, 20-2, . . . zn are stored in the memory 3.

Since the display operation of the information stored in the memory 3 is no different from the conventional device, a detailed explanation will be omitted here.

Next, the features of the present invention will be further explained with reference to the time chart of FIG. 2. In FIG.
Suppose that 2 were each like (Al)% (person 2). Time tostl, tz, ts of write clock 32
, t4, the signal 21-1 is recognized as existing at times tx, ts, and La as shown by (Bl),
Similarly, the signal 21-2 is transmitted at time t as shown in (B2).
z Sts and is recognized as existing and written to the memory 3.

As a result, the signals 21-1% 21-2 are respectively (Ci)
, (C2) is displayed on the display unit 4.

In the case of the conventional device, the x6 section in (A1) could not be detected as shown by the broken line in (C1), but it can be displayed according to the present invention.

In order to accurately display the input signal, it is convenient to always output a reset signal so that the display mode can be switched so as not to be held.

As explained above, the present invention makes the sampling period of input information shorter than the memory writing period and is configured to hold the sample result until it is written to the memory. This has the effect of displaying signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the signal display device according to the present invention, and the mX diagram shows an example of the time relationship between signals 30 and 340 shown in FIG. It is a time chart showing the relationship. 1--Input gate 2--Sample circuit 3--Memory 4--Display section S-Control section 6--Sample clock generation circuit 7--Memory control four clock generation circuit 8--Address counter 20-1.20 -2, -1・20- n-Human power signal 21
-1.21-2, ----21- n = input gate 1
The output of! 2-1.22-2, "'-22-n-・Output 23 of sample circuit 2-Reading information 24 of memory 3--Address information (material)...Sample clock 31--Reset signal 32--・・Memory write clock 33 ・・Address count signal ・・Memory read timing 35 ・・Threshold level specification 36 ・・・Address initial setting signal 37 ・・Display control signal 38 ・・・Memory write cycle specification patent Applicant: NEC Corporation

Claims (1)

[Claims] Means is provided to extract and hold the input signal at a cycle shorter than the cycle at which the input signal is written to the memory, and release the hold of the input signal in synchronization with a memory write clock, and the memory write cycle is also shorter. A signal display device configured to display a pulse input signal in the same time width as the memory write cycle.