JPS58100484U - Thyristor rectifier control circuit - Google Patents
Thyristor rectifier control circuitInfo
- Publication number
- JPS58100484U JPS58100484U JP19674681U JP19674681U JPS58100484U JP S58100484 U JPS58100484 U JP S58100484U JP 19674681 U JP19674681 U JP 19674681U JP 19674681 U JP19674681 U JP 19674681U JP S58100484 U JPS58100484 U JP S58100484U
- Authority
- JP
- Japan
- Prior art keywords
- control circuit
- thyristor
- thyristor rectifier
- rectifier control
- width pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Rectifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、同期信号によって幅パルスを制御する従来方
式を示すタイミングチャート図、第２図は、本考案の一
実施例による制御回路によって作動する相混合ブリッジ
整流回路、第３図は、本考案の一実施例による制御回路
の回路図、および第４図は、第３図の制御回路の動作を
説明するためのタイミングチャート図である。
３０・・・・・・インターロック回路、３１，３２゜３
３・・・・・・インバータ回路。
幕２図
未未″永 １ ’−
′θ」−
−展−３図 −FIG. 1 is a timing chart showing a conventional method of controlling width pulses by a synchronizing signal, FIG. 2 is a phase mixing bridge rectifier circuit operated by a control circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of the present invention. A circuit diagram of a control circuit according to an embodiment of the invention, and FIG. 4 is a timing chart diagram for explaining the operation of the control circuit of FIG. 3. 30...Interlock circuit, 31, 32゜3
3...Inverter circuit. Act 2, Figure 2, ``Ei 1 '- 'θ''- - Exhibition, Figure 3 -
Claims (1)
用いる多相サイリスタ整流器の制御回路において、 １相のサイリスタに幅パルスを供給して該サイリスタを
点弧させる際、前記幅パルスでもってそれまで他相の対
応サイリスタに供給されていた別の幅パルスを消滅させ
るインターロック回路を備えることを特徴とする制御回
路。[Claims for Utility Model Registration] In a control circuit for a multiphase thyristor rectifier that uses a width pulse having a fixed duration as a gate pulse, when the width pulse is supplied to a one-phase thyristor to fire the thyristor, A control circuit comprising an interlock circuit that uses a width pulse to extinguish another width pulse that has been supplied to a corresponding thyristor of another phase.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19674681U JPS58100484U (en) | 1981-12-28 | 1981-12-28 | Thyristor rectifier control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19674681U JPS58100484U (en) | 1981-12-28 | 1981-12-28 | Thyristor rectifier control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58100484U true JPS58100484U (en) | 1983-07-08 |
Family
ID=30109979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19674681U Pending JPS58100484U (en) | 1981-12-28 | 1981-12-28 | Thyristor rectifier control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58100484U (en) |
-
1981
- 1981-12-28 JP JP19674681U patent/JPS58100484U/en active Pending
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