JPS58133824U - switching regulator - Google Patents
switching regulatorInfo
- Publication number
- JPS58133824U JPS58133824U JP2898182U JP2898182U JPS58133824U JP S58133824 U JPS58133824 U JP S58133824U JP 2898182 U JP2898182 U JP 2898182U JP 2898182 U JP2898182 U JP 2898182U JP S58133824 U JPS58133824 U JP S58133824U
- Authority
- JP
- Japan
- Prior art keywords
- pulse width
- width modulator
- switching regulator
- output
- dead time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Dc-Dc Converters (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のスイッチングレギュレータ回路図、第２
図は本考案−実施例を示す回路図、第３図は第２図の要
部の詳細を示す回路図である。
３ニスイツチング素子、１２：第１のパルス幅変調器、
１３：瞬時停電検出回路、１４：デッドタイム制御回路
、１５：第２のパルス幅変調器、１６：ＡＮＤ回路。Figure 1 is a conventional switching regulator circuit diagram, Figure 2 is a circuit diagram of a conventional switching regulator.
The figure is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a circuit diagram showing details of the main part of FIG. 2. 3 switching element, 12: first pulse width modulator,
13: Momentary power failure detection circuit, 14: Dead time control circuit, 15: Second pulse width modulator, 16: AND circuit.
Claims (1)
れるスイッチングレギュレータでアッテ瞬時停電検出回
路とその検出出力により作動しソフトスタート素子によ
り制御されるデッドタイム制御回路と、この制御回路に
より制御され、その制御によるデッドタイム終了後にパ
ルス幅を零としてスタートする第２のパルス幅変調器と
、この第２のパルス幅変調器出力と前記第１に掲げたパ
ルス幅変調器出力とのＡＮＤ回路とを具備したことを特
徴とするスイッチングレギュレータ。A switching regulator whose switching element is conduction controlled by a pulse width modulator includes an instantaneous power failure detection circuit, a dead time control circuit that is activated by its detection output and controlled by a soft start element, and a dead time control circuit that is activated by the detection output and controlled by a soft start element. A second pulse width modulator that starts with a pulse width of zero after the dead time ends, and an AND circuit of the output of the second pulse width modulator and the output of the pulse width modulator listed in the first item. A switching regulator featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2898182U JPS58133824U (en) | 1982-03-03 | 1982-03-03 | switching regulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2898182U JPS58133824U (en) | 1982-03-03 | 1982-03-03 | switching regulator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58133824U true JPS58133824U (en) | 1983-09-09 |
Family
ID=30040791
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2898182U Pending JPS58133824U (en) | 1982-03-03 | 1982-03-03 | switching regulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58133824U (en) |
-
1982
- 1982-03-03 JP JP2898182U patent/JPS58133824U/en active Pending
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