JPS58131541U - timer device - Google Patents
timer deviceInfo
- Publication number
- JPS58131541U JPS58131541U JP2841682U JP2841682U JPS58131541U JP S58131541 U JPS58131541 U JP S58131541U JP 2841682 U JP2841682 U JP 2841682U JP 2841682 U JP2841682 U JP 2841682U JP S58131541 U JPS58131541 U JP S58131541U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- circuit
- keep relay
- detection signal
- drive circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Relay Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図においてaは1巻線キープリレーを用いた従来の
タイマ装置の回路図でbおよびCはその各部波形、第2
図においてaは2巻線キープリレーを用いた従来のタイ
マ装置の回路図でbはその各部波形、第3図は本考案の
1実施例に係るタイマ装置のブロック図、第4〜6図は
それぞれ第3図の装置のより具体的な実施例を示す回路
図、そして第7図は本考案のさらに他の実施例を示すブ
ロック図である。
2・・・・・・タイマ回路、3・・・・・・キープリレ
ー駆動回路、4・・・・・・レベル検出回路、5・・・
・・・ゲート回路。In Figure 1, a is a circuit diagram of a conventional timer device using a one-winding keep relay, b and C are waveforms of each part, and the second
In the figure, a is a circuit diagram of a conventional timer device using a two-winding keep relay, b is a waveform of each part, FIG. 3 is a block diagram of a timer device according to an embodiment of the present invention, and FIGS. 4 to 6 are FIG. 3 is a circuit diagram showing a more specific embodiment of the apparatus, and FIG. 7 is a block diagram showing still another embodiment of the present invention. 2...Timer circuit, 3...Keep relay drive circuit, 4...Level detection circuit, 5...
...Gate circuit.
Claims (1)
レベル検出回路と、この検出信号によって初期リセット
されるとともに予め設定された時間に従ってタイマ出力
を送出するタイマ回路と、このタイマ出力によってキー
プリレーをセットおよびリセットするキープリレー駆動
回路と、前記タイマ回路と前記キープリレー駆動回路と
の間に挿入され前記検出信号に従って前記キープリレー
駆動回路への前記タイマ出力の伝達を開閉制御するゲー
ト回路とを具備することを特徴とするタイマ装置。A level detection circuit that sends out a detection signal when the power supply voltage is lower than a predetermined voltage, a timer circuit that is initially reset by this detection signal and sends out a timer output according to a preset time, and a keep relay that uses this timer output. It includes a keep relay drive circuit that sets and resets, and a gate circuit that is inserted between the timer circuit and the keep relay drive circuit and controls opening/closing of transmission of the timer output to the keep relay drive circuit according to the detection signal. A timer device characterized by:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2841682U JPS58131541U (en) | 1982-03-02 | 1982-03-02 | timer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2841682U JPS58131541U (en) | 1982-03-02 | 1982-03-02 | timer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58131541U true JPS58131541U (en) | 1983-09-05 |
JPH0421232Y2 JPH0421232Y2 (en) | 1992-05-14 |
Family
ID=30040263
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2841682U Granted JPS58131541U (en) | 1982-03-02 | 1982-03-02 | timer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58131541U (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5043865A (en) * | 1973-08-21 | 1975-04-19 |
-
1982
- 1982-03-02 JP JP2841682U patent/JPS58131541U/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5043865A (en) * | 1973-08-21 | 1975-04-19 |
Also Published As
Publication number | Publication date |
---|---|
JPH0421232Y2 (en) | 1992-05-14 |
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