JPS5799766A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS5799766A JPS5799766A JP55176713A JP17671380A JPS5799766A JP S5799766 A JPS5799766 A JP S5799766A JP 55176713 A JP55176713 A JP 55176713A JP 17671380 A JP17671380 A JP 17671380A JP S5799766 A JPS5799766 A JP S5799766A
- Authority
- JP
- Japan
- Prior art keywords
- vth
- voltage
- substrate
- clamping
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/205—Substrate bias-voltage generators
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Nonlinear Science (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
PURPOSE:To prevent the variation of substrate bias generating voltage even when line voltage varies by mounting a clamping circuit at the output side of a substrate potential generating circuit and clamping the upper and lower limits or one side of the oscillating output of a drive circuit. CONSTITUTION:Rectangular waves are oscillated 201 at predetermined frequency, and supplied to the drive circuit 202. When the threshold voltage of the FET201 of the voltage clamping circuit 210 is Vth, the upper limit of the output of the drive circuit 202 is clamped to VR+Vth, and fed to a coupling capacity 203. The potential of a node 207 is changed into the rectangular waves, which have the +Vth maximum value and the minimum value of Vth-(VR+Vth)=-VR, by the clamping action of an FET205, electrons are scooped out to a substrate 208 through an FET204 by the negative voltage, and the substrate voltage VR under a stationary state shifts only by the threshold value Vth of the FET and reaches approximately Vth-VR. Accordingly, when VR is set to value suffuiciently lower than a variation section of the line voltage Vcc, the substrate bias generating voltage is fixed to (Vth-VR) without regard to the variation of Vcc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176713A JPS5799766A (en) | 1980-12-11 | 1980-12-11 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55176713A JPS5799766A (en) | 1980-12-11 | 1980-12-11 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5799766A true JPS5799766A (en) | 1982-06-21 |
Family
ID=16018452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55176713A Pending JPS5799766A (en) | 1980-12-11 | 1980-12-11 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5799766A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914665A (en) * | 1982-07-16 | 1984-01-25 | Nec Corp | Semiconductor device |
| JPS63304656A (en) * | 1987-05-15 | 1988-12-12 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | Protective system of complementary metal oxide semiconductor integrated circuit |
| US6125075A (en) * | 1985-07-22 | 2000-09-26 | Hitachi, Ltd. | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
-
1980
- 1980-12-11 JP JP55176713A patent/JPS5799766A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5914665A (en) * | 1982-07-16 | 1984-01-25 | Nec Corp | Semiconductor device |
| US6125075A (en) * | 1985-07-22 | 2000-09-26 | Hitachi, Ltd. | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| US6363029B1 (en) | 1985-07-22 | 2002-03-26 | Hitachi, Ltd. | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| US6970391B2 (en) | 1985-07-22 | 2005-11-29 | Renesas Technology Corporation | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| US7002856B2 (en) | 1986-07-18 | 2006-02-21 | Renesas Technology Corporation | Semiconductor device incorporating internal power supply for compensating for deviation in operating condition and fabrication process conditions |
| JPS63304656A (en) * | 1987-05-15 | 1988-12-12 | アドバンスト・マイクロ・ディバイシズ・インコーポレーテッド | Protective system of complementary metal oxide semiconductor integrated circuit |
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