JPS5798176A - Storage controlling unit - Google Patents

Storage controlling unit

Info

Publication number
JPS5798176A
JPS5798176A JP55172263A JP17226380A JPS5798176A JP S5798176 A JPS5798176 A JP S5798176A JP 55172263 A JP55172263 A JP 55172263A JP 17226380 A JP17226380 A JP 17226380A JP S5798176 A JPS5798176 A JP S5798176A
Authority
JP
Japan
Prior art keywords
processing
register
adder
contents
address calculation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55172263A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6141021B2 (enrdf_load_stackoverflow
Inventor
Masaaki Inao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55172263A priority Critical patent/JPS5798176A/ja
Publication of JPS5798176A publication Critical patent/JPS5798176A/ja
Publication of JPS6141021B2 publication Critical patent/JPS6141021B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1027—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
    • G06F12/1036—Address translation using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] for multiple virtual address spaces, e.g. segmentation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP55172263A 1980-12-06 1980-12-06 Storage controlling unit Granted JPS5798176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55172263A JPS5798176A (en) 1980-12-06 1980-12-06 Storage controlling unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55172263A JPS5798176A (en) 1980-12-06 1980-12-06 Storage controlling unit

Publications (2)

Publication Number Publication Date
JPS5798176A true JPS5798176A (en) 1982-06-18
JPS6141021B2 JPS6141021B2 (enrdf_load_stackoverflow) 1986-09-12

Family

ID=15938648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55172263A Granted JPS5798176A (en) 1980-12-06 1980-12-06 Storage controlling unit

Country Status (1)

Country Link
JP (1) JPS5798176A (enrdf_load_stackoverflow)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01111017U (enrdf_load_stackoverflow) * 1988-01-20 1989-07-26
JPH02233U (enrdf_load_stackoverflow) * 1988-06-15 1990-01-05

Also Published As

Publication number Publication date
JPS6141021B2 (enrdf_load_stackoverflow) 1986-09-12

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