JPS5795736A - Two-way data transmission device - Google Patents
Two-way data transmission deviceInfo
- Publication number
- JPS5795736A JPS5795736A JP17178280A JP17178280A JPS5795736A JP S5795736 A JPS5795736 A JP S5795736A JP 17178280 A JP17178280 A JP 17178280A JP 17178280 A JP17178280 A JP 17178280A JP S5795736 A JPS5795736 A JP S5795736A
- Authority
- JP
- Japan
- Prior art keywords
- transmission
- data
- clock
- transceivers
- places
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Computer Networks & Wireless Communication (AREA)
- Bidirectional Digital Transmission (AREA)
Abstract
PURPOSE:To reduce the number of transmission lines, by providing one control pulse generator and a required number of transceivers in separated places A and B respectively and by controlling places A and B by a transmission/receiving mode designating signal so that one of them is set to the receiving side when the other is the transmission side. CONSTITUTION:A control pulse generator CPG and transceivers TR1-TR4 are provided in places A and B respectively, and control pulse generators CPG are connected by two timing clock lines La and Lb, and transceivers are connected to each other by data transmission lines L1-L4 respectively. A clock CLK, which determines the period of transmission data bits and a clock CLK2 which determines the data transmission start timing are inputted to the control pulse generator CPG to generate transmission clocks Qa-Qc, a receiving clock -CLK1, and a transmission/receiving mode designating signal Qd repeating H and L levels. The transceiver TR has a data selector 62, which transmits N-bit parallel data in serial by clocks Qa-Qc, and a shift register, which outputs received serial data as parallel data by the clock -CLK1, and inserts or removes in inverter 50 into or from the circuit of the signal Qd, thus controlling transceivers in places A and B so that one is set to the receiving side when the other is the transmission side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17178280A JPS5795736A (en) | 1980-12-05 | 1980-12-05 | Two-way data transmission device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17178280A JPS5795736A (en) | 1980-12-05 | 1980-12-05 | Two-way data transmission device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5795736A true JPS5795736A (en) | 1982-06-14 |
Family
ID=15929576
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17178280A Pending JPS5795736A (en) | 1980-12-05 | 1980-12-05 | Two-way data transmission device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5795736A (en) |
-
1980
- 1980-12-05 JP JP17178280A patent/JPS5795736A/en active Pending
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