JPS5794823A - Bus connecting system - Google Patents
Bus connecting systemInfo
- Publication number
- JPS5794823A JPS5794823A JP17129780A JP17129780A JPS5794823A JP S5794823 A JPS5794823 A JP S5794823A JP 17129780 A JP17129780 A JP 17129780A JP 17129780 A JP17129780 A JP 17129780A JP S5794823 A JPS5794823 A JP S5794823A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- master
- slave
- order
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4027—Coupling between buses using bus bridges
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Abstract
PURPOSE:To realize the control of connection between high-order and low-order buses and furthermore to eliminate the ideas like systems 0, 1 and the others, by connecting the low-order master bus to the high-order master bus and the low- order slave bus to the low-order slave bus, respectively. CONSTITUTION:A main display FF set instruction of a bus controller BC100 of system 0 sets a man display FF101 and at the same time resets a main display FF201 of a bus controller BC200 of system 1. The output of the main FF is connected to a master/slave display line 300' of a bus 300 of system 0 for the controller BC100 and to a master/slave display line 301' of a bus 301 of system 1 for the controller BC200, respectively. The master/slave displays of systems 0 and 1 are exclusively set, and the buses set to the master/slave lines 1 and 0 are used as the master and slave buses respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17129780A JPS5794823A (en) | 1980-12-04 | 1980-12-04 | Bus connecting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17129780A JPS5794823A (en) | 1980-12-04 | 1980-12-04 | Bus connecting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5794823A true JPS5794823A (en) | 1982-06-12 |
Family
ID=15920676
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17129780A Pending JPS5794823A (en) | 1980-12-04 | 1980-12-04 | Bus connecting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5794823A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0319663A2 (en) * | 1987-12-07 | 1989-06-14 | Bull HN Information Systems Inc. | Bidirectional control signalling bus interface apparatus for transmitting signals between two bus system |
-
1980
- 1980-12-04 JP JP17129780A patent/JPS5794823A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0319663A2 (en) * | 1987-12-07 | 1989-06-14 | Bull HN Information Systems Inc. | Bidirectional control signalling bus interface apparatus for transmitting signals between two bus system |
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