JPS5793433A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS5793433A JPS5793433A JP16805380A JP16805380A JPS5793433A JP S5793433 A JPS5793433 A JP S5793433A JP 16805380 A JP16805380 A JP 16805380A JP 16805380 A JP16805380 A JP 16805380A JP S5793433 A JPS5793433 A JP S5793433A
- Authority
- JP
- Japan
- Prior art keywords
- output
- data
- message
- transfer
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computer And Data Communications (AREA)
- Communication Control (AREA)
- Financial Or Insurance-Related Operations Such As Payment And Settlement (AREA)
Abstract
PURPOSE:To omit the transfer of information in unnecessary status by a terminal device, by adding information which indicates whether the transfer request of the next data is performed when the data is received in transferring the data from a central device or after waiting the end of output processing. CONSTITUTION:A control bit is added at the head of an output message from a central device, and when this is 1, it shows a mode not requiring the transfer of terminal status information, i.e., in case of special message such as telegraphic message exchange, and when it is 0, it means a normal message, i.e., a mode requiring the transfer of terminal status information. This output data passes through a channel 50 and enters a transmission/reception circuit 31, a program controlling mechanism 32 is started and the usage state of an output buffer 36 is checked. If it is in use, the output message is stored in an output buffer 33 by waiting the end, and the controlling mechanism 32 waites for the data from the buffer 33 after the output of an output device is possible, and when the control bit is checked and it is zero, the end report is waited from the output device, and when it is 1, the output request of the next data is transmitted to the central device for the advancing processing.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55168053A JPS5939770B2 (en) | 1980-12-01 | 1980-12-01 | Data transfer method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55168053A JPS5939770B2 (en) | 1980-12-01 | 1980-12-01 | Data transfer method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5793433A true JPS5793433A (en) | 1982-06-10 |
JPS5939770B2 JPS5939770B2 (en) | 1984-09-26 |
Family
ID=15860950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55168053A Expired JPS5939770B2 (en) | 1980-12-01 | 1980-12-01 | Data transfer method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5939770B2 (en) |
-
1980
- 1980-12-01 JP JP55168053A patent/JPS5939770B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5939770B2 (en) | 1984-09-26 |
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