JPS5792944A - Transmitting device - Google Patents

Transmitting device

Info

Publication number
JPS5792944A
JPS5792944A JP55168674A JP16867480A JPS5792944A JP S5792944 A JPS5792944 A JP S5792944A JP 55168674 A JP55168674 A JP 55168674A JP 16867480 A JP16867480 A JP 16867480A JP S5792944 A JPS5792944 A JP S5792944A
Authority
JP
Japan
Prior art keywords
pulse
auxiliary
counter
output
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55168674A
Other languages
Japanese (ja)
Inventor
Tadahiko Nakamura
Tatsuo Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TOHO SEISAKUJIYO KK
TOHO SEISAKUSHO KK
TOUHOU SEISAKUJIYO KK
Original Assignee
TOHO SEISAKUJIYO KK
TOHO SEISAKUSHO KK
TOUHOU SEISAKUJIYO KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TOHO SEISAKUJIYO KK, TOHO SEISAKUSHO KK, TOUHOU SEISAKUJIYO KK filed Critical TOHO SEISAKUJIYO KK
Priority to JP55168674A priority Critical patent/JPS5792944A/en
Publication of JPS5792944A publication Critical patent/JPS5792944A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To prevent the rise and the fall of a synchronizing pulse from dulling, by adding an auxiliary pulse of the opposite polarity continuously at the rise of the fall of the synchronizing pulse and transmitting them in case that the synchronizing pulse of the positive or negative polarity is transmitted. CONSTITUTION:An output P1 of an oscillator Aa is applied to an input terminal I of a counter Ab. The counter Ab divides the output P1 to generate a pulse P2 for modulation from an output terminal Qa. A signal S1 (0,1-n) is generated from an output terminal Ob. A control circuit Ad generates a control signal S2 in accordance with the signal S1 to control a data generating circuit Ac. The data generating circuit Ac generates a reset pulse P30 and an auxiliary pulse P'30 of the polarity opposite to that of the pulse P30 continuously. Further, count pulses P31-P3n and auxiliary pulses P'31-P'3n of the polarity opposite to that of these count pulses are generated continously. The reset pulse P30 and the auxiliary pulse P'30 are applied to a reset terminal R of the counter Ab. Data D1-D16 are inputted to a modulating circuit Ae and are outputted to a transmission line L as time division data signals D1'-D16'.
JP55168674A 1980-11-29 1980-11-29 Transmitting device Pending JPS5792944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55168674A JPS5792944A (en) 1980-11-29 1980-11-29 Transmitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55168674A JPS5792944A (en) 1980-11-29 1980-11-29 Transmitting device

Publications (1)

Publication Number Publication Date
JPS5792944A true JPS5792944A (en) 1982-06-09

Family

ID=15872378

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55168674A Pending JPS5792944A (en) 1980-11-29 1980-11-29 Transmitting device

Country Status (1)

Country Link
JP (1) JPS5792944A (en)

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