JPS5791027A - Offset compensating circuit for coder - Google Patents
Offset compensating circuit for coderInfo
- Publication number
- JPS5791027A JPS5791027A JP16670580A JP16670580A JPS5791027A JP S5791027 A JPS5791027 A JP S5791027A JP 16670580 A JP16670580 A JP 16670580A JP 16670580 A JP16670580 A JP 16670580A JP S5791027 A JPS5791027 A JP S5791027A
- Authority
- JP
- Japan
- Prior art keywords
- offset
- coder
- adder
- inputted
- analog signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To obtain an output strong against noise and crosstalk, by automatically calculating and storing an offset value and making offset compensation at the application of input of coder actually, based on the preset value for offset set to a half the digital resolution. CONSTITUTION:A referene voltage is inputted to a voltage adder 1 from an offset gate 2, and the adder 1 inputs the reference voltage to a coder 5. Next, the gate 2 is disconnected from a positive input terminal of the adder 1. On the other hand, a stored data in an offset data memory 4 is inputted to an offset circuit 3 to form a corresponding analog signal and inputted to a negative terminal of the adder 1. The adder 1 takes the difference between a normal analog signal and an offset analog signal being the output of the circuit 3 and the difference is inputted to a coder 5. The coder 5 converts the input difference into a digital code and the digital code after conversion is outputted from the output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16670580A JPS5791027A (en) | 1980-11-28 | 1980-11-28 | Offset compensating circuit for coder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16670580A JPS5791027A (en) | 1980-11-28 | 1980-11-28 | Offset compensating circuit for coder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5791027A true JPS5791027A (en) | 1982-06-07 |
Family
ID=15836224
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16670580A Pending JPS5791027A (en) | 1980-11-28 | 1980-11-28 | Offset compensating circuit for coder |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5791027A (en) |
-
1980
- 1980-11-28 JP JP16670580A patent/JPS5791027A/en active Pending
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