JPS55164976A - Processing system for analog digital signal - Google Patents

Processing system for analog digital signal

Info

Publication number
JPS55164976A
JPS55164976A JP7064879A JP7064879A JPS55164976A JP S55164976 A JPS55164976 A JP S55164976A JP 7064879 A JP7064879 A JP 7064879A JP 7064879 A JP7064879 A JP 7064879A JP S55164976 A JPS55164976 A JP S55164976A
Authority
JP
Japan
Prior art keywords
switch
signal
vref
digital signal
during
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7064879A
Other languages
Japanese (ja)
Inventor
Michinobu Ohata
Toshihiko Matsumura
Masao Yamazawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7064879A priority Critical patent/JPS55164976A/en
Publication of JPS55164976A publication Critical patent/JPS55164976A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE: To enable to add the correction to the A/D conversion only with a simple circuit, by adding the addition and subtraction for control signal at sampling mode for input analog signal, in charge re-distribution system.
CONSTITUTION: The input analog signal Ain is charged to the capacitor group C1WCn during the time when the sampling switch 11 is ON. During this first sampling period, one switch among the switches 13-1W13-n is connected to the reference voltage source + Vref or - Vref. Further, when the output of the comparator 12 is 1, the logic circuit 15 connects the contact of the switch 14 to - Vref via the switch decoder 17, and when 0, to + Vref. Accordingly, during the sampling period, with the operation of one switch among the switches 13-1W13-n and the switch 14 corresponding to the control digital signal CD, the addition and subtraction of the control analog signal specified with the signal CD to the signal Ain is made and the digital signal Dowt can be obtained with correction added.
COPYRIGHT: (C)1980,JPO&Japio
JP7064879A 1979-06-07 1979-06-07 Processing system for analog digital signal Pending JPS55164976A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7064879A JPS55164976A (en) 1979-06-07 1979-06-07 Processing system for analog digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7064879A JPS55164976A (en) 1979-06-07 1979-06-07 Processing system for analog digital signal

Publications (1)

Publication Number Publication Date
JPS55164976A true JPS55164976A (en) 1980-12-23

Family

ID=13437672

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7064879A Pending JPS55164976A (en) 1979-06-07 1979-06-07 Processing system for analog digital signal

Country Status (1)

Country Link
JP (1) JPS55164976A (en)

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