JPS5789348A - Modulating and demodulating device - Google Patents

Modulating and demodulating device

Info

Publication number
JPS5789348A
JPS5789348A JP16730780A JP16730780A JPS5789348A JP S5789348 A JPS5789348 A JP S5789348A JP 16730780 A JP16730780 A JP 16730780A JP 16730780 A JP16730780 A JP 16730780A JP S5789348 A JPS5789348 A JP S5789348A
Authority
JP
Japan
Prior art keywords
circuit
forcedly
interoffice
guard bit
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16730780A
Other languages
Japanese (ja)
Other versions
JPS6318905B2 (en
Inventor
Kiyoshi Fujita
Shigeru Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16730780A priority Critical patent/JPS5789348A/en
Publication of JPS5789348A publication Critical patent/JPS5789348A/en
Publication of JPS6318905B2 publication Critical patent/JPS6318905B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To eliminate the transmission of a reference bit to improve the transmission efficiency, by using an interoffice guard bit to release forcedly differential encoding and decoding circuits in the transmitting and receiving terminal. CONSTITUTION:In the transmission side, the signal from a timing pulse generating circuit 6 is used to detect the time of a interoffice guard bit in a guard bit detecting circuit 13, and the PCM pulse train from a transmission memory circuit 1 is forcedly released in a differential code forcedly releasing circuit 12 by the output control pulse. In the receiving side, the signal from a timing pulse generating circuit 11 is used to detect the time of a receiving-side interoffice guard bit in an interoffice guard bit detecting circuit 15, and by the output control pulse, a differential decoding circuit 9 is forcedly released by a differential decoding forcedly releasing circuit 14.
JP16730780A 1980-11-25 1980-11-25 Modulating and demodulating device Granted JPS5789348A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16730780A JPS5789348A (en) 1980-11-25 1980-11-25 Modulating and demodulating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16730780A JPS5789348A (en) 1980-11-25 1980-11-25 Modulating and demodulating device

Publications (2)

Publication Number Publication Date
JPS5789348A true JPS5789348A (en) 1982-06-03
JPS6318905B2 JPS6318905B2 (en) 1988-04-20

Family

ID=15847315

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16730780A Granted JPS5789348A (en) 1980-11-25 1980-11-25 Modulating and demodulating device

Country Status (1)

Country Link
JP (1) JPS5789348A (en)

Also Published As

Publication number Publication date
JPS6318905B2 (en) 1988-04-20

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