JPS5787608A - Offset rejecting system cuased at output of differential amplifier - Google Patents

Offset rejecting system cuased at output of differential amplifier

Info

Publication number
JPS5787608A
JPS5787608A JP55163335A JP16333580A JPS5787608A JP S5787608 A JPS5787608 A JP S5787608A JP 55163335 A JP55163335 A JP 55163335A JP 16333580 A JP16333580 A JP 16333580A JP S5787608 A JPS5787608 A JP S5787608A
Authority
JP
Japan
Prior art keywords
offset
output
differential amplifier
signal
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55163335A
Other languages
Japanese (ja)
Inventor
Nobuhiko Tsuji
Keijiro Nakamura
Koichi Endo
Toshiyoshi Hamada
Keiichi Ishida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Fuji Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd, Fuji Electric Manufacturing Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP55163335A priority Critical patent/JPS5787608A/en
Priority to US06/318,000 priority patent/US4420564A/en
Publication of JPS5787608A publication Critical patent/JPS5787608A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To avoid the fluctuation of offset by time and to supply the signal component only at all times to an A/D converter, by storing an offset component to a storage means in the form of a digital signal. CONSTITUTION:An analog input signal from a measuring electrode 1 is amplified at a differential amplifier 32, inputted to an A/D converter 33 and converted into a digital signal. This converted digital signal is stored in a memory via a buffer 34 and a data bus and given to a data latch 36 for storage. On the other hand, when the analog input signal is zero, the offset being the output of the amplifier 32 is in A/D conversion and stored to the data latch 36, and the stored offset is read out and converted into an analog signal by a D/A converter 35 and given to one input of the differential amplifier 32 to output the signal component only.
JP55163335A 1980-11-21 1980-11-21 Offset rejecting system cuased at output of differential amplifier Pending JPS5787608A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP55163335A JPS5787608A (en) 1980-11-21 1980-11-21 Offset rejecting system cuased at output of differential amplifier
US06/318,000 US4420564A (en) 1980-11-21 1981-11-04 Blood sugar analyzer having fixed enzyme membrane sensor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55163335A JPS5787608A (en) 1980-11-21 1980-11-21 Offset rejecting system cuased at output of differential amplifier

Publications (1)

Publication Number Publication Date
JPS5787608A true JPS5787608A (en) 1982-06-01

Family

ID=15771898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55163335A Pending JPS5787608A (en) 1980-11-21 1980-11-21 Offset rejecting system cuased at output of differential amplifier

Country Status (1)

Country Link
JP (1) JPS5787608A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59147508A (en) * 1983-02-07 1984-08-23 テクトロニツクス・インコーポレイテツド Offset equilibrating method and device of dc amplifier
US4806875A (en) * 1988-05-11 1989-02-21 Maxim Integrated Products Precision operational amplifier

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108077A (en) * 1979-02-12 1980-08-19 Varian Associates Zero reference and offset compensation circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55108077A (en) * 1979-02-12 1980-08-19 Varian Associates Zero reference and offset compensation circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59147508A (en) * 1983-02-07 1984-08-23 テクトロニツクス・インコーポレイテツド Offset equilibrating method and device of dc amplifier
JPH0528002B2 (en) * 1983-02-07 1993-04-23 Tektronix Inc
US4806875A (en) * 1988-05-11 1989-02-21 Maxim Integrated Products Precision operational amplifier

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