JPS5783931A - Output buffer circuit - Google Patents

Output buffer circuit

Info

Publication number
JPS5783931A
JPS5783931A JP55160217A JP16021780A JPS5783931A JP S5783931 A JPS5783931 A JP S5783931A JP 55160217 A JP55160217 A JP 55160217A JP 16021780 A JP16021780 A JP 16021780A JP S5783931 A JPS5783931 A JP S5783931A
Authority
JP
Japan
Prior art keywords
level signal
output buffer
buffer circuit
inputted
turns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55160217A
Other languages
Japanese (ja)
Inventor
Makoto Noda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55160217A priority Critical patent/JPS5783931A/en
Publication of JPS5783931A publication Critical patent/JPS5783931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To prevent a latch-up state by employing a push-pull circuit, constituted by connecting N channel MOS transistors (TR), as the final stage of an output buffer consisting of complementary MOS TRs. CONSTITUTION:At the final stage of an output buffer circuit, N channel MOS TRs Q4 and Q3 are connected in series between a power source Vcc and an earth point. As an H-level signal is inputted to an input terminal 11, the H-level signal is applied to the gate of the Q3, and an L-level signal inverted by an inverter 22 is also applied to the Q4 to turn on the Q3, so that an output terminal 22 is held at a level L. When an L-level signal is inputted to the input terminal 11, the Q4 turns on and the Q3 turns off, outputting an H-level signal to the output terminal 22.
JP55160217A 1980-11-14 1980-11-14 Output buffer circuit Pending JPS5783931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55160217A JPS5783931A (en) 1980-11-14 1980-11-14 Output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55160217A JPS5783931A (en) 1980-11-14 1980-11-14 Output buffer circuit

Publications (1)

Publication Number Publication Date
JPS5783931A true JPS5783931A (en) 1982-05-26

Family

ID=15710256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55160217A Pending JPS5783931A (en) 1980-11-14 1980-11-14 Output buffer circuit

Country Status (1)

Country Link
JP (1) JPS5783931A (en)

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