JPS5783914A - Digital limiter - Google Patents

Digital limiter

Info

Publication number
JPS5783914A
JPS5783914A JP55159486A JP15948680A JPS5783914A JP S5783914 A JPS5783914 A JP S5783914A JP 55159486 A JP55159486 A JP 55159486A JP 15948680 A JP15948680 A JP 15948680A JP S5783914 A JPS5783914 A JP S5783914A
Authority
JP
Japan
Prior art keywords
input data
data
threshold
sign bit
adder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55159486A
Other languages
Japanese (ja)
Inventor
Mitsuyoshi Hashida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55159486A priority Critical patent/JPS5783914A/en
Publication of JPS5783914A publication Critical patent/JPS5783914A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G7/00—Volume compression or expansion in amplifiers
    • H03G7/007—Volume compression or expansion in amplifiers of digital or coded signals

Landscapes

  • Control Of Amplification And Gain Control (AREA)
  • Tone Control, Compression And Expansion, Limiting Amplitude (AREA)

Abstract

PURPOSE:To increase a dynamic range by selecting a sign bit which corresponding to that of input data when the sign bits of the input data and threshold- level data are equal. CONSTITUTION:A gate 10 is provided for exclusive OR between input data and threshold-level data, and the output data of an adder 1 which adds the input data and threshould-level data mutually or the input data is selected by a selector 11 corresponding to the output of the gate 10. When the input data and threshold-level data has the same sign, the selector 11 selects and applies the sign bit of the input data to a D type FF3, where the sign bit is latched. When the input data and threshold-level data have different signs, the adder 1 never causes an overflow, so the sign bit of the output data of the adder 1 is selected by the selector 11 and applied to the D type FF3.
JP55159486A 1980-11-14 1980-11-14 Digital limiter Pending JPS5783914A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55159486A JPS5783914A (en) 1980-11-14 1980-11-14 Digital limiter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55159486A JPS5783914A (en) 1980-11-14 1980-11-14 Digital limiter

Publications (1)

Publication Number Publication Date
JPS5783914A true JPS5783914A (en) 1982-05-26

Family

ID=15694816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55159486A Pending JPS5783914A (en) 1980-11-14 1980-11-14 Digital limiter

Country Status (1)

Country Link
JP (1) JPS5783914A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2607990A1 (en) * 1986-12-09 1988-06-10 Sony Corp DIGITAL LIMITER CIRCUIT

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2607990A1 (en) * 1986-12-09 1988-06-10 Sony Corp DIGITAL LIMITER CIRCUIT

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