JPS5782300A - Dynamic memory system with software error rewriting control system - Google Patents

Dynamic memory system with software error rewriting control system

Info

Publication number
JPS5782300A
JPS5782300A JP56114532A JP11453281A JPS5782300A JP S5782300 A JPS5782300 A JP S5782300A JP 56114532 A JP56114532 A JP 56114532A JP 11453281 A JP11453281 A JP 11453281A JP S5782300 A JPS5782300 A JP S5782300A
Authority
JP
Japan
Prior art keywords
dynamic memory
software error
control system
rewriting control
memory system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56114532A
Other languages
English (en)
Other versions
JPS6230665B2 (ja
Inventor
Bii Jiyonson Robaato
Emu Nibiii Jiyunia Chiesutaa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of JPS5782300A publication Critical patent/JPS5782300A/ja
Publication of JPS6230665B2 publication Critical patent/JPS6230665B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/106—Correcting systematically all correctable errors, i.e. scrubbing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Retry When Errors Occur (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP56114532A 1980-07-25 1981-07-23 Dynamic memory system with software error rewriting control system Granted JPS5782300A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/172,485 US4369510A (en) 1980-07-25 1980-07-25 Soft error rewrite control system

Publications (2)

Publication Number Publication Date
JPS5782300A true JPS5782300A (en) 1982-05-22
JPS6230665B2 JPS6230665B2 (ja) 1987-07-03

Family

ID=22627881

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56114532A Granted JPS5782300A (en) 1980-07-25 1981-07-23 Dynamic memory system with software error rewriting control system

Country Status (7)

Country Link
US (1) US4369510A (ja)
JP (1) JPS5782300A (ja)
AU (1) AU546314B2 (ja)
CA (1) CA1168364A (ja)
DE (1) DE3128729C2 (ja)
FR (1) FR2487561B1 (ja)
IT (1) IT1171392B (ja)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60500979A (ja) * 1983-03-30 1985-06-27 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド メモリへのアクセスを制御するための装置
JPS61123957A (ja) * 1984-11-21 1986-06-11 Nec Corp 記憶装置
JPH0194600A (ja) * 1987-10-07 1989-04-13 Fujitsu Ltd メモリ管理方式
JP2012256414A (ja) * 2011-06-09 2012-12-27 Samsung Electronics Co Ltd エラー訂正回路を具備したオンチップ・データ・スクラビング装置及び方法

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4493081A (en) * 1981-06-26 1985-01-08 Computer Automation, Inc. Dynamic memory with error correction on refresh
US4535455A (en) * 1983-03-11 1985-08-13 At&T Bell Laboratories Correction and monitoring of transient errors in a memory system
FR2552916B1 (fr) * 1983-09-29 1988-06-10 Thomas Alain File d'attente asynchrone a empilement de registres
US4604750A (en) * 1983-11-07 1986-08-05 Digital Equipment Corporation Pipeline error correction
JPS649756U (ja) * 1987-07-09 1989-01-19
US4965717A (en) * 1988-12-09 1990-10-23 Tandem Computers Incorporated Multiple processor system having shared memory with private-write capability
US5473770A (en) * 1993-03-02 1995-12-05 Tandem Computers Incorporated Fault-tolerant computer system with hidden local memory refresh
US5495491A (en) * 1993-03-05 1996-02-27 Motorola, Inc. System using a memory controller controlling an error correction means to detect and correct memory errors when and over a time interval indicated by registers in the memory controller
US6065146A (en) * 1996-10-21 2000-05-16 Texas Instruments Incorporated Error correcting memory
US6085271A (en) * 1998-04-13 2000-07-04 Sandcraft, Inc. System bus arbitrator for facilitating multiple transactions in a computer system
US6701480B1 (en) * 2000-03-08 2004-03-02 Rockwell Automation Technologies, Inc. System and method for providing error check and correction in memory systems
US9459960B2 (en) 2005-06-03 2016-10-04 Rambus Inc. Controller device for use with electrically erasable programmable memory chip with error detection and retry modes of operation
US7831882B2 (en) 2005-06-03 2010-11-09 Rambus Inc. Memory system with error detection and retry modes of operation
US7562285B2 (en) * 2006-01-11 2009-07-14 Rambus Inc. Unidirectional error code transfer for a bidirectional data link
US20070271495A1 (en) * 2006-05-18 2007-11-22 Ian Shaeffer System to detect and identify errors in control information, read data and/or write data
US8352805B2 (en) 2006-05-18 2013-01-08 Rambus Inc. Memory error detection
JP4791912B2 (ja) * 2006-08-31 2011-10-12 株式会社東芝 不揮発性半導体記憶装置及び不揮発性記憶システム
US8429470B2 (en) * 2010-03-10 2013-04-23 Micron Technology, Inc. Memory devices, testing systems and methods
US8347154B2 (en) * 2010-09-21 2013-01-01 International Business Machines Corporation Use of hashing function to distinguish random and repeat errors in a memory system
KR101178562B1 (ko) * 2010-11-02 2012-09-03 에스케이하이닉스 주식회사 커맨드 제어회로 및 이를 포함하는 반도체 메모리 장치 및 커맨드 제어방법
EP3776207B1 (en) 2018-03-26 2023-08-09 Rambus Inc. Command/address channel error detection

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4072853A (en) * 1976-09-29 1978-02-07 Honeywell Information Systems Inc. Apparatus and method for storing parity encoded data from a plurality of input/output sources
JPS5381036A (en) * 1976-12-27 1978-07-18 Hitachi Ltd Error correction-detection system
US4183096A (en) * 1978-05-25 1980-01-08 Bell Telephone Laboratories, Incorporated Self checking dynamic memory system
US4185323A (en) * 1978-07-20 1980-01-22 Honeywell Information Systems Inc. Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations
US4216541A (en) * 1978-10-05 1980-08-05 Intel Magnetics Inc. Error repairing method and apparatus for bubble memories
US4255808A (en) * 1979-04-19 1981-03-10 Sperry Corporation Hard or soft cell failure differentiator

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60500979A (ja) * 1983-03-30 1985-06-27 アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド メモリへのアクセスを制御するための装置
JPH0471223B2 (ja) * 1983-03-30 1992-11-13 Advanced Micro Devices Inc
JPS61123957A (ja) * 1984-11-21 1986-06-11 Nec Corp 記憶装置
JPH0194600A (ja) * 1987-10-07 1989-04-13 Fujitsu Ltd メモリ管理方式
JP2012256414A (ja) * 2011-06-09 2012-12-27 Samsung Electronics Co Ltd エラー訂正回路を具備したオンチップ・データ・スクラビング装置及び方法

Also Published As

Publication number Publication date
DE3128729A1 (de) 1982-03-11
FR2487561B1 (fr) 1990-02-16
JPS6230665B2 (ja) 1987-07-03
US4369510A (en) 1983-01-18
IT1171392B (it) 1987-06-10
DE3128729C2 (de) 1985-03-07
FR2487561A1 (fr) 1982-01-29
AU7231281A (en) 1982-01-28
IT8148909A0 (it) 1981-07-15
CA1168364A (en) 1984-05-29
AU546314B2 (en) 1985-08-29

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