JPS5775376A - Analog arithmetic circuit - Google Patents
Analog arithmetic circuitInfo
- Publication number
- JPS5775376A JPS5775376A JP55150174A JP15017480A JPS5775376A JP S5775376 A JPS5775376 A JP S5775376A JP 55150174 A JP55150174 A JP 55150174A JP 15017480 A JP15017480 A JP 15017480A JP S5775376 A JPS5775376 A JP S5775376A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- sum
- equal
- signals
- checking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06G—ANALOGUE COMPUTERS
- G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
- G06G7/02—Details not covered by G06G7/04 - G06G7/10, e.g. monitoring, construction, maintenance
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Testing And Monitoring For Control Systems (AREA)
Abstract
PURPOSE:To realize an on-line checking of an analog circuit, by checking whether the monitor signal is equal to a prescribed value or not with no special operation nor any limit of instrumentation and under the using state. CONSTITUTION:A resistance R101 is put between the input terminal of an operational amplifier OP3 and a Zener diode ZD3, and the produced signal v5 for a checking is supplied to a resistance R104. At the same time, signals v1 and v2 are applied to resistances R102 and R103 respectively. As a result, a monitor signal VM equal to the sum of signals v1, and v2 and v5 is produced from an adder comprising resistances R102, R103, R104 and R105, a capacitor 101 and an operational amplifier OP4. When the sum of the signal v5 and the Zener voltage of a Zener diode ZD3 is less than the saturated voltage of the OP3, the signal v5 is equal to a signal obtained by inverting the polarity of the sum of signals v1 and v2 plus bias viltages vB and VS. As a result, the signal VM is equal to the sum VB and VS which are set at the constant value, and accordingly the signal VM also becomes constant. The constant value of the signal VM indicates that an analog arithmetic circuit is working in the normal way.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55150174A JPS5775376A (en) | 1980-10-28 | 1980-10-28 | Analog arithmetic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55150174A JPS5775376A (en) | 1980-10-28 | 1980-10-28 | Analog arithmetic circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5775376A true JPS5775376A (en) | 1982-05-11 |
JPH0157832B2 JPH0157832B2 (en) | 1989-12-07 |
Family
ID=15491112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55150174A Granted JPS5775376A (en) | 1980-10-28 | 1980-10-28 | Analog arithmetic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5775376A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4416727Y1 (en) * | 1967-06-17 | 1969-07-19 |
-
1980
- 1980-10-28 JP JP55150174A patent/JPS5775376A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4416727Y1 (en) * | 1967-06-17 | 1969-07-19 |
Also Published As
Publication number | Publication date |
---|---|
JPH0157832B2 (en) | 1989-12-07 |
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