JPS5773403A - Remote monitor controller - Google Patents
Remote monitor controllerInfo
- Publication number
- JPS5773403A JPS5773403A JP14893580A JP14893580A JPS5773403A JP S5773403 A JPS5773403 A JP S5773403A JP 14893580 A JP14893580 A JP 14893580A JP 14893580 A JP14893580 A JP 14893580A JP S5773403 A JPS5773403 A JP S5773403A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- supplied
- output
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
PURPOSE:To avoid an erroneous output of control which is caused when a microprocessor (MPU) has a faulty working, by processing the address, data and writing signals sent from the MPU through a delaying, 1-shot and AND circuits respectively. CONSTITUTION:The address signal A sent from an MPU1 is detected by a detector 2 and then supplied to an AND circuit 4 along with a writing signal D. The data D given from the MPU1 is fetched to a register 3 by the output signal of the circuit 4. An AND5 is secured between the data D and the output of the circuit 4 to produce a signal 9 of period T1. The signal 9 is supplied to a 1-shot circuit 6. The output (b) of the circuit 6 is inverted 7 and supplied to an on-delay circuit 8 having a delay time T2 shorter than the period T1 to obtain a signal (c). An AND9 is secured between the output (d) of the register 3 and the signals (a) and (c) to produce a signal (e). This signal (e) is supplied to an off-delay circuit 10 having a delay time T3 longer than the T1 to produce a signal (g). An AND12 is secured between the signals (g) and (d) to deliver a signal R'. At the same time, the signal (a) is inverted 13 and supplied to an on-delay circuit 11 haing a delay time T3. Then the register 3 is cleared by a delayed signal (h).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14893580A JPS5773403A (en) | 1980-10-24 | 1980-10-24 | Remote monitor controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14893580A JPS5773403A (en) | 1980-10-24 | 1980-10-24 | Remote monitor controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5773403A true JPS5773403A (en) | 1982-05-08 |
Family
ID=15463943
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14893580A Pending JPS5773403A (en) | 1980-10-24 | 1980-10-24 | Remote monitor controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5773403A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9982692B2 (en) | 2012-10-18 | 2018-05-29 | Fujikura Rubber Ltd. | Air cylinder apparatus equipped with fall prevention mechanism, and fall prevention mechanism for air cylinder apparatus |
-
1980
- 1980-10-24 JP JP14893580A patent/JPS5773403A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9982692B2 (en) | 2012-10-18 | 2018-05-29 | Fujikura Rubber Ltd. | Air cylinder apparatus equipped with fall prevention mechanism, and fall prevention mechanism for air cylinder apparatus |
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