JPS57733A - Path controlling system for interruption for reporting input and output operation completion of input and output bus device - Google Patents

Path controlling system for interruption for reporting input and output operation completion of input and output bus device

Info

Publication number
JPS57733A
JPS57733A JP7433780A JP7433780A JPS57733A JP S57733 A JPS57733 A JP S57733A JP 7433780 A JP7433780 A JP 7433780A JP 7433780 A JP7433780 A JP 7433780A JP S57733 A JPS57733 A JP S57733A
Authority
JP
Japan
Prior art keywords
input
interruption
actuation
bus
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7433780A
Other languages
Japanese (ja)
Other versions
JPS6213707B2 (en
Inventor
Hirokazu Kasashima
Hiroaki Nakanishi
Ryoichi Takamatsu
Takayuki Morioka
Masakazu Okada
Hideyuki Hara
Toshihisa Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7433780A priority Critical patent/JPS57733A/en
Priority to GB8116665A priority patent/GB2077468B/en
Priority to DE19813122076 priority patent/DE3122076A1/en
Priority to US06/270,549 priority patent/US4468733A/en
Publication of JPS57733A publication Critical patent/JPS57733A/en
Publication of JPS6213707B2 publication Critical patent/JPS6213707B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To exercise easily path control in reporting interruption for input and output operation completion, by storing the existence of actuation from a processor in a storing means by input and output equipment numbers of an interbus coupling part where a bus loop is connected, and then by performing processing.
CONSTITUTION: Through respective CPU stations ST63WST65, CPUs 51W53 are connected to Y bus loops 54W56, and through I/Os ST66WST72, I/Os 73W79 are connected to the Y bus loops 54W56, an X bus loop 57, and a Z bus loop 58. Each of interbus coupling parts 59W61 has a means of storing the existence of actuation from a CPU by I/O numbers; when a transfer information word sent from an I/O has a frame showing end interruption, the storing means is retrieved on the basis of an I/O number in the frame and only when the contents of the storing means show the existence of actuation, an end interruption frame is sent to a bus loop close to the corresponding CPU. Then, the contents of the storing means at this time are changed to show nonexistence of actuation, thereby exercising path control in end reporting interruption.
COPYRIGHT: (C)1982,JPO&Japio
JP7433780A 1980-06-04 1980-06-04 Path controlling system for interruption for reporting input and output operation completion of input and output bus device Granted JPS57733A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP7433780A JPS57733A (en) 1980-06-04 1980-06-04 Path controlling system for interruption for reporting input and output operation completion of input and output bus device
GB8116665A GB2077468B (en) 1980-06-04 1981-06-01 Multi-computer system with plural serial bus loops
DE19813122076 DE3122076A1 (en) 1980-06-04 1981-06-03 MULTIPLE COMPUTER SYSTEM
US06/270,549 US4468733A (en) 1980-06-04 1981-06-04 Multi-computer system with plural serial bus loops

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7433780A JPS57733A (en) 1980-06-04 1980-06-04 Path controlling system for interruption for reporting input and output operation completion of input and output bus device

Publications (2)

Publication Number Publication Date
JPS57733A true JPS57733A (en) 1982-01-05
JPS6213707B2 JPS6213707B2 (en) 1987-03-28

Family

ID=13544198

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7433780A Granted JPS57733A (en) 1980-06-04 1980-06-04 Path controlling system for interruption for reporting input and output operation completion of input and output bus device

Country Status (1)

Country Link
JP (1) JPS57733A (en)

Also Published As

Publication number Publication date
JPS6213707B2 (en) 1987-03-28

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