JPS5771050A - Overlapped microinstruction control system - Google Patents

Overlapped microinstruction control system

Info

Publication number
JPS5771050A
JPS5771050A JP56121314A JP12131481A JPS5771050A JP S5771050 A JPS5771050 A JP S5771050A JP 56121314 A JP56121314 A JP 56121314A JP 12131481 A JP12131481 A JP 12131481A JP S5771050 A JPS5771050 A JP S5771050A
Authority
JP
Japan
Prior art keywords
overlapped
control system
microinstruction control
microinstruction
overlapped microinstruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56121314A
Other languages
English (en)
Other versions
JPS6230651B2 (ja
Inventor
Edouin Raatei Aachii
Rairu Inguruburekuto Kenesu
Richiyaado Karubesuto Donarudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of JPS5771050A publication Critical patent/JPS5771050A/ja
Publication of JPS6230651B2 publication Critical patent/JPS6230651B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/28—Enhancement of operational speed, e.g. by using several microcontrol devices operating in parallel

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
JP56121314A 1980-07-31 1981-07-31 Overlapped microinstruction control system Granted JPS5771050A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/174,035 US4376976A (en) 1980-07-31 1980-07-31 Overlapped macro instruction control system

Publications (2)

Publication Number Publication Date
JPS5771050A true JPS5771050A (en) 1982-05-01
JPS6230651B2 JPS6230651B2 (ja) 1987-07-03

Family

ID=22634520

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56121314A Granted JPS5771050A (en) 1980-07-31 1981-07-31 Overlapped microinstruction control system

Country Status (4)

Country Link
US (1) US4376976A (ja)
EP (1) EP0045634B1 (ja)
JP (1) JPS5771050A (ja)
DE (1) DE3166481D1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603044A (ja) * 1983-04-05 1985-01-09 バロ−ス・コ−ポレ−シヨン 制御装置
JPS603043A (ja) * 1983-04-05 1985-01-09 ユニシス・コーポレイション システムインタ−フエイスユニツト
JPH04309131A (ja) * 1991-02-08 1992-10-30 Internatl Business Mach Corp <Ibm> 命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0097725B1 (de) * 1982-06-08 1986-05-14 Ibm Deutschland Gmbh Einrichtung im Befehlswerk eines mikroprogrammgesteuerten Prozessors zur direkten hardwaregesteuerten Ausführung bestimmter Instruktionen
US4594658A (en) * 1983-04-05 1986-06-10 Burroughs Corporation Hierarchy of control stores for overlapped data transmission
US4800486A (en) * 1983-09-29 1989-01-24 Tandem Computers Incorporated Multiple data patch CPU architecture
USRE34052E (en) * 1984-05-31 1992-09-01 International Business Machines Corporation Data processing system with CPU register to register data transfers overlapped with data transfer to and from main storage
US4791560A (en) * 1985-07-31 1988-12-13 Unisys Corporation Macro level control of an activity switch in a scientific vector processor which processor requires an external executive control program
JPH0743648B2 (ja) * 1985-11-15 1995-05-15 株式会社日立製作所 情報処理装置
US5001624A (en) * 1987-02-13 1991-03-19 Harrell Hoffman Processor controlled DMA controller for transferring instruction and data from memory to coprocessor
US5185870A (en) * 1987-04-10 1993-02-09 Tandem Computers, Inc, System to determine if modification of first macroinstruction to execute in fewer clock cycles
US5005118A (en) * 1987-04-10 1991-04-02 Tandem Computers Incorporated Method and apparatus for modifying micro-instructions using a macro-instruction pipeline
DE3855524T2 (de) * 1987-06-19 1997-02-06 Hitachi Ltd Arithmetik-Parallelverarbeitungseinheit und zugehöriger Kompilator
JP2982875B2 (ja) * 1987-12-28 1999-11-29 株式会社日立製作所 スレーブ制御装置
JP2806524B2 (ja) * 1988-03-04 1998-09-30 日本電気株式会社 ベクトル演算命令発行制御方法
AU7305491A (en) * 1990-01-29 1991-08-21 Teraplex, Inc. Architecture for minimal instruction set computing system
EP0477599A3 (en) * 1990-09-26 1993-11-10 Siemens Ag Control store for a processor comprising several processing elements
US5363495A (en) * 1991-08-26 1994-11-08 International Business Machines Corporation Data processing system with multiple execution units capable of executing instructions out of sequence
US5426783A (en) * 1992-11-02 1995-06-20 Amdahl Corporation System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set
CA2123442A1 (en) * 1993-09-20 1995-03-21 David S. Ray Multiple execution unit dispatch with instruction dependency
US5673427A (en) * 1994-03-01 1997-09-30 Intel Corporation Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue
US5537629A (en) * 1994-03-01 1996-07-16 Intel Corporation Decoder for single cycle decoding of single prefixes in variable length instructions
US5630083A (en) * 1994-03-01 1997-05-13 Intel Corporation Decoder for decoding multiple instructions in parallel
US5559974A (en) * 1994-03-01 1996-09-24 Intel Corporation Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation
US5566298A (en) * 1994-03-01 1996-10-15 Intel Corporation Method for state recovery during assist and restart in a decoder having an alias mechanism
US5586277A (en) * 1994-03-01 1996-12-17 Intel Corporation Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders
US5600806A (en) * 1994-03-01 1997-02-04 Intel Corporation Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer
US5758116A (en) * 1994-09-30 1998-05-26 Intel Corporation Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions
US5867701A (en) * 1995-06-12 1999-02-02 Intel Corporation System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow
US5815724A (en) * 1996-03-29 1998-09-29 Intel Corporation Method and apparatus for controlling power consumption in a microprocessor
US6789186B1 (en) * 2000-02-18 2004-09-07 Hewlett-Packard Development Company, L.P. Method and apparatus to reduce penalty of microcode lookup
US7698539B1 (en) 2003-07-16 2010-04-13 Banning John P System and method of instruction modification
US9122465B2 (en) * 2011-12-06 2015-09-01 International Business Machines Corporation Programmable microcode unit for mapping plural instances of an instruction in plural concurrently executed instruction streams to plural microcode sequences in plural memory partitions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168749A (ja) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS53108254A (en) * 1977-03-02 1978-09-20 Nec Corp Information processor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51144142A (en) * 1975-06-06 1976-12-10 Hitachi Ltd Information processing
US4107774A (en) * 1976-10-04 1978-08-15 Honeywell Information Systems Inc. Microprogram splatter return apparatus

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5168749A (ja) * 1974-12-11 1976-06-14 Fujitsu Ltd
JPS53108254A (en) * 1977-03-02 1978-09-20 Nec Corp Information processor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603044A (ja) * 1983-04-05 1985-01-09 バロ−ス・コ−ポレ−シヨン 制御装置
JPS603043A (ja) * 1983-04-05 1985-01-09 ユニシス・コーポレイション システムインタ−フエイスユニツト
JPH0630060B2 (ja) * 1983-04-05 1994-04-20 バロ−ス・コ−ポレ−シヨン システムインタ−フエイスユニツト
JPH04309131A (ja) * 1991-02-08 1992-10-30 Internatl Business Mach Corp <Ibm> 命令群用マイクロコード生成装置及びコンピュータにおける組合せ装置

Also Published As

Publication number Publication date
DE3166481D1 (en) 1984-11-08
EP0045634B1 (en) 1984-10-03
EP0045634A1 (en) 1982-02-10
JPS6230651B2 (ja) 1987-07-03
US4376976A (en) 1983-03-15

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