JPS5771036A - Input and output controller - Google Patents

Input and output controller

Info

Publication number
JPS5771036A
JPS5771036A JP14665480A JP14665480A JPS5771036A JP S5771036 A JPS5771036 A JP S5771036A JP 14665480 A JP14665480 A JP 14665480A JP 14665480 A JP14665480 A JP 14665480A JP S5771036 A JPS5771036 A JP S5771036A
Authority
JP
Japan
Prior art keywords
input
address
output equipment
work
absolute address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14665480A
Other languages
Japanese (ja)
Inventor
Yoshiki Sudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14665480A priority Critical patent/JPS5771036A/en
Publication of JPS5771036A publication Critical patent/JPS5771036A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To improve the processing performance of an input and output equipment by achieving the flexible allotment of a work area, by specifying an identification number and a relative address. CONSTITUTION:Some input and output equipment 2-i, when an access is allowed to work area assigned to the input and output equipment 2-i in a storage circuit 9, transfers specified information to in input and output controller 1, and then a work-area starting absolute address is outputted from an address converting circuit 7 in response to its identification code and added to a relative address to generate a work-area absolute address; and it is used to specify the absolute address of the storage circuit 9, and data is read and requested through a data bus 3 to be transferred to the input and output equipment 2-i. Therefore, accurate access is attained without knowing the absolute address of its work area.
JP14665480A 1980-10-20 1980-10-20 Input and output controller Pending JPS5771036A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14665480A JPS5771036A (en) 1980-10-20 1980-10-20 Input and output controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14665480A JPS5771036A (en) 1980-10-20 1980-10-20 Input and output controller

Publications (1)

Publication Number Publication Date
JPS5771036A true JPS5771036A (en) 1982-05-01

Family

ID=15412604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14665480A Pending JPS5771036A (en) 1980-10-20 1980-10-20 Input and output controller

Country Status (1)

Country Link
JP (1) JPS5771036A (en)

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