JPS5760738A - Frequency synthesizer - Google Patents

Frequency synthesizer

Info

Publication number
JPS5760738A
JPS5760738A JP55136427A JP13642780A JPS5760738A JP S5760738 A JPS5760738 A JP S5760738A JP 55136427 A JP55136427 A JP 55136427A JP 13642780 A JP13642780 A JP 13642780A JP S5760738 A JPS5760738 A JP S5760738A
Authority
JP
Japan
Prior art keywords
power
state
under
frequency divider
multiplier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55136427A
Other languages
Japanese (ja)
Inventor
Sadayuki Nishiki
Akio Sasaki
Hiroto Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Panasonic Mobile Communications Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Matsushita Communication Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Matsushita Communication Industrial Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55136427A priority Critical patent/JPS5760738A/en
Publication of JPS5760738A publication Critical patent/JPS5760738A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
    • H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To increase the frequency division ratio of a frequency divider and the multiplication ratio of a multiplier to improve the precision at the nonoperation time, by providing an oscillator, which oscillates an independent frequency under the power off state, when the synthesizer is operated intermittently for the purpose of reducing power consumption of the synthesizer. CONSTITUTION:The first VCO4 and the second VCO26 operated by the same control voltage are provided, and a PLL circuit is constituted by VCOs 4 and 26. A switch 21 is connected to a variable frequency divider 5 under the power on-state of the frequency divider 5 of the PLL circuit and is connected to a multiplier 24 under the power off-state. After the output of a variable frequency divider 25 is multiplied in the multiplier 24 by L by this connection, the output is inputted to a phase comparator 2, and a feedback loop through the VCO26 is formed under the power off-state. Inputs of the VCO4 under the power on-state and the power off- state are made equal to each other approximately, thereby enhancing the frequency precision of the output voltage of an output terminal 7 of the PLL circuit.
JP55136427A 1980-09-29 1980-09-29 Frequency synthesizer Pending JPS5760738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55136427A JPS5760738A (en) 1980-09-29 1980-09-29 Frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55136427A JPS5760738A (en) 1980-09-29 1980-09-29 Frequency synthesizer

Publications (1)

Publication Number Publication Date
JPS5760738A true JPS5760738A (en) 1982-04-12

Family

ID=15174889

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55136427A Pending JPS5760738A (en) 1980-09-29 1980-09-29 Frequency synthesizer

Country Status (1)

Country Link
JP (1) JPS5760738A (en)

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