JPS5752238A - Radio receiving circuit - Google Patents
Radio receiving circuitInfo
- Publication number
- JPS5752238A JPS5752238A JP12749280A JP12749280A JPS5752238A JP S5752238 A JPS5752238 A JP S5752238A JP 12749280 A JP12749280 A JP 12749280A JP 12749280 A JP12749280 A JP 12749280A JP S5752238 A JPS5752238 A JP S5752238A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- pulse
- signal
- inputting
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D3/00—Demodulation of angle-, frequency- or phase- modulated oscillations
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
PURPOSE:To obtain a radio receiving circuit which requires no adjustment, and has high accuracy and high reliability, by directly executing a digital conversion of a receiving high-frequency modulation or phase modulation signal. CONSTITUTION:A timing controlling circuit 43 for inputting a signal from a local oscillator 4, and a frequency digital converting circuit 12 for inputting a reference clock S2 from the circuit 43 and a signal from an intermediate frequency amplifier 7 are provided on the radio receiving circuit. On the circuit 12, a differentiating circuit 31 for sampling an input pulse number signal S1 of a pulse rate H, by an input clock of a pulse rate F from a timing generating circuit 34 for inputting the clock S2, a comparing circuit 32 to which an output of this circuit 31 is inputted, a counter 33 for counting an output pulse of this circuit 32, and a multiplier ML35 for receiving the pulse from the circuit 34 and generating a pulse in accordance with a counting value of the counter 33 are provided. The circuit 32 compares outputs of the circuit 31 and the ML35, increases or decreases the counting value of the counter 33 in accordance with a result of said comparison, and generates an output having magnitude corresponding to the frequency of the input pulse number signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12749280A JPS5752238A (en) | 1980-09-13 | 1980-09-13 | Radio receiving circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12749280A JPS5752238A (en) | 1980-09-13 | 1980-09-13 | Radio receiving circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5752238A true JPS5752238A (en) | 1982-03-27 |
Family
ID=14961291
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12749280A Pending JPS5752238A (en) | 1980-09-13 | 1980-09-13 | Radio receiving circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5752238A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS647729A (en) * | 1987-06-30 | 1989-01-11 | Pioneer Electronic Corp | Digital tuner |
-
1980
- 1980-09-13 JP JP12749280A patent/JPS5752238A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS647729A (en) * | 1987-06-30 | 1989-01-11 | Pioneer Electronic Corp | Digital tuner |
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