JPS5750038A - Programmable controller - Google Patents

Programmable controller

Info

Publication number
JPS5750038A
JPS5750038A JP55124306A JP12430680A JPS5750038A JP S5750038 A JPS5750038 A JP S5750038A JP 55124306 A JP55124306 A JP 55124306A JP 12430680 A JP12430680 A JP 12430680A JP S5750038 A JPS5750038 A JP S5750038A
Authority
JP
Japan
Prior art keywords
card
byte
data
programmable controller
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55124306A
Other languages
Japanese (ja)
Inventor
Yoshifumi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55124306A priority Critical patent/JPS5750038A/en
Publication of JPS5750038A publication Critical patent/JPS5750038A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
    • G05B19/054—Input/output
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/10—Plc systems
    • G05B2219/11—Plc I-O input output
    • G05B2219/1188—Detection of inserted boards, inserting extra memory, availability of boards
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Automation & Control Theory (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To arrange an I/O card having an optional number of bytes, at a free position, in a programmable controller containing plural I/O cards which send and receive a data 10 and from the CPU part. CONSTITUTION:Before a data is sent and received between a CPU part 10 and each I/O card 12, the CPU part 10 reads out from each I/O card a card number of each I/O card 12, and also a byte number corresponding to each byte of each I/O card 12, to a card number storage part 16a of an RAM16, and a byte number storage part 16b, respectively, and stores as shown in the table. For instance, in order to write a data in the third byte of an I/O card 12-1 corresponding to an address (m)=5, when an address 5 of 16 is designated from 10, a card number designating signal 400 and a byte number designating signal 300 are outputted through a decoder 20 in accordance with the table, and subsequently, when a write signal 102 is applied from 20, the data on a data bus 14 is written in the third byte of the I/O card 12-1.
JP55124306A 1980-09-08 1980-09-08 Programmable controller Pending JPS5750038A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55124306A JPS5750038A (en) 1980-09-08 1980-09-08 Programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55124306A JPS5750038A (en) 1980-09-08 1980-09-08 Programmable controller

Publications (1)

Publication Number Publication Date
JPS5750038A true JPS5750038A (en) 1982-03-24

Family

ID=14882063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55124306A Pending JPS5750038A (en) 1980-09-08 1980-09-08 Programmable controller

Country Status (1)

Country Link
JP (1) JPS5750038A (en)

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