JPS5748842A - Frame synchronizing circuit - Google Patents

Frame synchronizing circuit

Info

Publication number
JPS5748842A
JPS5748842A JP55124294A JP12429480A JPS5748842A JP S5748842 A JPS5748842 A JP S5748842A JP 55124294 A JP55124294 A JP 55124294A JP 12429480 A JP12429480 A JP 12429480A JP S5748842 A JPS5748842 A JP S5748842A
Authority
JP
Japan
Prior art keywords
auxiliary frame
auxiliary
pattern
distortion
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55124294A
Other languages
English (en)
Other versions
JPS6028172B2 (ja
Inventor
Masao Furubayashi
Yoshimi Kenjo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Technical Research and Development Institute of Japan Defence Agency
Original Assignee
NEC Corp
Technical Research and Development Institute of Japan Defence Agency
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Technical Research and Development Institute of Japan Defence Agency, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55124294A priority Critical patent/JPS6028172B2/ja
Publication of JPS5748842A publication Critical patent/JPS5748842A/ja
Publication of JPS6028172B2 publication Critical patent/JPS6028172B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP55124294A 1980-09-08 1980-09-08 フレ−ム同期回路 Expired JPS6028172B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55124294A JPS6028172B2 (ja) 1980-09-08 1980-09-08 フレ−ム同期回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55124294A JPS6028172B2 (ja) 1980-09-08 1980-09-08 フレ−ム同期回路

Publications (2)

Publication Number Publication Date
JPS5748842A true JPS5748842A (en) 1982-03-20
JPS6028172B2 JPS6028172B2 (ja) 1985-07-03

Family

ID=14881764

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55124294A Expired JPS6028172B2 (ja) 1980-09-08 1980-09-08 フレ−ム同期回路

Country Status (1)

Country Link
JP (1) JPS6028172B2 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6166434A (ja) * 1984-09-10 1986-04-05 Matsushita Tsushin Kogyo Kk 分周回路
JPS63133731A (ja) * 1986-11-26 1988-06-06 Nec Corp フレ−ム同期回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6166434A (ja) * 1984-09-10 1986-04-05 Matsushita Tsushin Kogyo Kk 分周回路
JPS63133731A (ja) * 1986-11-26 1988-06-06 Nec Corp フレ−ム同期回路

Also Published As

Publication number Publication date
JPS6028172B2 (ja) 1985-07-03

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